Modelling and Simulation of Hetero-Dielectric Surrounding Gate TFET

Article Preview

Abstract:

Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influence of short channel effects and the leakage current, a surrounding gate with three different work function materials is used. Stacked dielectric or hetero-dielectric is used to improve the ON current of device. Performance of the device has been analyzed with different gate material lengths such as 10 nm, 15 nm and 20 nm. The developed 2-D mathematical model is used to obtain results like drain current, surface potential and electrical field in the vertical and lateral direction. From the results, a reduction in the device limitations is inferred and the leakage current is also considerably reduced. It has been found from the presented results that the proposed device structure Tri Material Cylindrical Gate Tunnel FET (TM CG TFET) provides the improved ON state current (10-3A/µm) and reduced OFF state current (10-14A/µm). The accuracy of the results and characteristics of the device are evaluated using TCAD simulations.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

47-58

Citation:

Online since:

April 2020

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2020 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] Kranti, A., Haldar, S., and Gupta, R. S. (2001). An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET.  Microelectronics Journal, 32(4), 305-313. https://doi.org/10.1016/S0026-2692(01)00008-8.

DOI: 10.1016/s0026-2692(01)00008-8

Google Scholar

[2] Kranti, A., Haldar, S., and Gupta, R. S. (2001). Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectronic Engineering, 56(3-4), 241-259. https://doi.org/10.1016/S0167-317(00) 00419-6.

DOI: 10.1016/s0167-9317(00)00419-6

Google Scholar

[3] Dubey, S., Santra, A., Saramekala, G., Kumar, M., and Tiwari, P. K. (2013). An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs. IEEE Transactions on Nanotechnology, 12(5),766-774. https://doi.org/10.1109/TNANO.2013.2273805.

DOI: 10.1109/tnano.2013.2273805

Google Scholar

[4] Oh, S. H., Monroe, D., and Hergenrother, J. M. (2000). Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE electron device letters, 21(9), 445-447.

DOI: 10.1109/55.863106

Google Scholar

[5] Gupta, S. K., and Baishya, S. (2012). Modelling and simulation of triple metal cylindrical surround gate MOSFETs for reduced short channel effects. International Journal of Soft Computing and Engineering (IJSCE), 2(2), 214-221.

Google Scholar

[6] Ghosh, P., Haldar, S., Gupta, R. S., and Gupta, M. (2012). Analytical modelling and simulation for dual metal gate stack architecture (DMGSA) cylindrical/surrounded gate MOSFET. JSTS: Journal of Semiconductor Technology and Science, 12(4), 458-466.

DOI: 10.5573/jsts.2012.12.4.458

Google Scholar

[7] Pratap, Y., Ghosh, P., Haldar, S., Gupta, R. S., and Gupta, M. (2014). An analytical subthreshold current modelling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering. Microelectronics Journal, 45(4), 408-415. https://doi.org/10.1016/j.mejo.2014.01.015.

DOI: 10.1016/j.mejo.2014.01.015

Google Scholar

[8] Tiwari, P. K., Dubey, S., Singh, M., and Jit, S. (2010). A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors. Journal of Applied Physics, 108(7), 074508. https://doi.org/10.1063/1.3488605.

DOI: 10.1063/1.3488605

Google Scholar

[9] Kumar, M.J., Orouji, A.A., and Dhakad, H. (2006). New dual-material SG nanoscale MOSFET: analytical threshold-voltage model. IEEE transactions on Electron Devices, 53(4), 920-922.

DOI: 10.1109/ted.2006.870422

Google Scholar

[10] Kane, E. O. (1961). Theory of tunneling. Journal of applied Physics, 32(1), 83-91. http://dx.doi.org/10.1063/1.1735965.

Google Scholar

[11] TCAD Sentarus Device User Guide, Synopsys Inc.,Version D-2010.03.

Google Scholar

[12] Vanitha, P., Samuel, T. A., and Nirmal, D. (2019). A new 2 D mathematical modelling of surrounding gate triple material tunnel FET using halo engineering for enhanced drain current. AEU-International Journal of Electronics and Communications, 99, 34-39. https://doi.org/10.1016/j.aeue.2018.11.013.

DOI: 10.1016/j.aeue.2018.11.013

Google Scholar

[13] Arun Samuel, T. S., Balamurugan, N. B., Bhuvaneswari, S., Sharmila, D., and Padmapriya, K. (2014). Analytical modelling and simulation of single-gate SOI TFET for low-power applications. International Journal of Electronics, 101(6), 779-788. https://doi.org/10.1080/00207217.2013.796544.

DOI: 10.1080/00207217.2013.796544

Google Scholar

[14] Verhulst, A. S., Sorée, B., Leonelli, D., Vandenberghe, W. G., and Groeseneken, G. (2010). Modelling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. Journal of Applied Physics, 107(2),024518. https://doi.org/10.1063/1.3277044.

DOI: 10.1063/1.3277044

Google Scholar

[15] Saurabh, S., and Kumar, M. J. (2010). Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE transactions on Electron Devices, 58(2), 404-410. 10.1109/TED.2010.2093142.

DOI: 10.1109/ted.2010.2093142

Google Scholar

[16] Ajayan, J., Nirmal, D., Prajoon, P., and Pravin, J. C. (2017). Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics Speed applications.AEU-International Journal of Electronics and Communications, 99, 130-38. https://doi.org/10.1016/j.aeue.2017.06.004.

DOI: 10.1016/j.aeue.2017.06.004

Google Scholar

[17] Priya, G. L., and Balamurugan, N. B. (2019). New dual material double gate junctionless Tunnel FET:Subthreshold modelling and simulation AEU-International Journal of Elect -ronics and Communications. 99-130-138. https://doi.org/10.1016/j.aeue.2018.11.037.

DOI: 10.1016/j.aeue.2018.11.037

Google Scholar