Interconnect Design Challenges in Nano CMOS Circuit

Abstract:

In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

• Periodical: Key Engineering Materials (Volume 470)
• Pages: 224-230
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.470.224
• Online since: February 2011
• Authors: Kazuya Masu, Shuhei Amakawa, Hiroyuki Ito, Noboru Ishihara
• Keywords: CMOS, Interconnect, On-Chip Transmission Line Interconnect, Scaling, Wire Length Distribution

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