Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs

Toshiro Hiramoto; Takuya Saraya; Chi Ho Lee

doi:10.4028/www.scientific.net/KEM.470.214

Paper Titles

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Influences of Carrier Transport on Drain-Current Variability of MOSFETs
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Resistive Switching in NiO Bilayer Films with Different Crystallinity Layers
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Analysis of Threshold Voltage Variations in Fin Field Effect Transistors
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Capture/Emission Processes of Carriers in Heterointerface Traps Observed in the Transient Charge-Pumping Characteristics of SiGe/Si-Hetero-Channel pMOSFETs
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Quasi-Ballistic Transport in Nano-Scale Devices: Boundary Layer, Potential Fluctuation, and Coulomb Interaction
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Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs
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Discrete Dopant Effects on Threshold Voltage Variation in Double-Gate and Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors
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Interconnect Design Challenges in Nano CMOS Circuit
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HomeKey Engineering MaterialsKey Engineering Materials Vol. 470Effect of Back Bias on Variability in Intrinsic...

Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs

Abstract:

The threshold voltage (Vth) variability in fully depleted SOI MOSFETs with intrinsic channel and ultrathin buried oxide under back bias voltage (Vbs) is extensively investigated by three dimensional device simulation. It is found that the Vth variability increases only slightly by applying negative Vbs by the effect of random dopant fluctuation (RDF) in the substrate, while the Vth variability is severely degraded by applying positive Vbs by the effect of the back interface inversion. As a result, there is a certain value of Vbs around 0 V where the Vth variability is minimized.

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Periodical:

Key Engineering Materials (Volume 470)

Pages:

214-217

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.470.214

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Online since:

February 2011

Authors:

Toshiro Hiramoto, Takuya Saraya, Chi Ho Lee

Keywords:

Dopant, Fully Depleted, Impurity, MOSFET, Random, RDF, SOI, Variability

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