A High-Performance Closed-Loop Fourth-Order Sigma-Delta Micro-Machined Accelerometer

Article Preview

Abstract:

In this paper a high-performance closed-loop fourth-order sigma-delta (ΣΔ) micro-accelerometer is presented. After a introduction of sigma-delta accelerometer, system-level analysis and design of a fourth-order sigma-delta micro-accelerometer is given. The simulation result shows that an accelerometer with 107dB signal to noise ratio (SNR) and 17.5 bits effective number of bits (ENOB) is achieved. Through the root locus analysis, it is got that accelerometer is stable when quantization gain is bigger than 0.262. The accelerometer gets a good linearity and it becomes overload when input signal level is greater than -5dBFS.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

134-138

Citation:

Online since:

February 2012

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2012 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] N. Yazid: Micro-g Silicon Accelerometers with High Performance CMOS Interface Circuitry, Ph. D dissertation, the University of Michigan (1999).

Google Scholar

[2] B. K. Amini: A Mixed-signal Low-noise Sigma-delta Interface IC for Integrated Sub-micro-gravity Capacitive SOI Accelerometers, Ph. D dissertation, Georgia Institute of Technology (2006).

Google Scholar

[3] Y. F. Dong, M. Kraft, C. Gollasch, and W. Redman-white: A High-performance Accelerometer With A Fifth-order Sigma-delta Modulator, Journal of Micromechanics and Microengineering, 15(2005)S22-S29.

DOI: 10.1088/0960-1317/15/7/004

Google Scholar

[4] S. R. Norsworthy, R. Schreier,G. C. Temes, Delta-Sigma Data Converters - Theory, Design and Simulation, IEEE Press(1996), chapter 5.

DOI: 10.1109/9780470544358

Google Scholar

[5] R. t. Baird and T. S. Fiez: Stability Analysis of High-Order Delta-Sigma Modulation for ADC's, Analog and digital signal processing, January 1994, vol. 41 No. 1.

DOI: 10.1109/82.275660

Google Scholar