Effect of Rapid Thermal Annealing on the Structural Evolution and Electrical Property of Gold Films Deposited on Silicon

Article Preview

Abstract:

An investigation of the electrical and microstructural properties of gold (Au)/p-type silicon (Si) contact was performed as a function of rapid thermal annealing (RTA) temperatures. Au films reacted with Si and produced Au2Si and Au3Si phases during the deposition of the films at room temperature. The electrical properties of the Au contact to p-type Si degraded with increasing RTA temperature. Such a degradation of the electrical properties could be associated with the degradation of the surface and interface morphology caused by the formation of Au-silicide clusters. The RTA process at 500 °C led to an increase in the size of the Au-silicide Island. This led to the further degradation of the electrical properties after annealing at 500 °C.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

97-101

Citation:

Online since:

February 2017

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2017 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] H. Cetin, B. Sahin, E. Ayyildiz, A. Turut, The barrier-height inhomogeneity in identically prepared H-terminated Ti/p-Si Schottky barrier diodes, Semicond. Sci. Technol. 19 (2004) 1113-1116.

DOI: 10.1088/0268-1242/19/9/007

Google Scholar

[2] J. F. Chang, T. F. Young, Y. L. Yang, H. Y. Ueng, T. C. Chang, Silicide formation of Au thin films on (100) Si during annealingOriginal Research Article, Mater. Chem. Phys. 83 (2004) 199-203.

DOI: 10.1016/s0254-0584(03)00240-2

Google Scholar

[3] C. R. Chen, L. J. Chen, Structural evolution and atomic structure of ultrahigh vacuum deposited Au thin films on silicon at low temperatures, Appl. Surf. Sci. 92 (1996) 507-512.

DOI: 10.1016/0169-4332(95)00286-3

Google Scholar

[4] C. R. Chen, L. J. Chen, Morphological evolution of the low‐temperature oxidation of silicon with a gold overlayer, J. Appl. Phys. 78 (1995) 919-925.

DOI: 10.1063/1.360283

Google Scholar

[5] K. Sekar, G. Kuri, P. V. Satyam, B. Sundaravel, D. P. Mahapatra, B. N. Dev, Shape transition in the epitaxial growth of gold silicide in Au thin films on Si(111)Phys. Rev. B. 51 (1995) 14330-14336.

DOI: 10.1103/physrevb.51.14330

Google Scholar

[6] T. Nakayama, S. Itaya, D. Murayama, Nano-scale view of atom intermixing at metal/semiconductor interfaces, J. Phys. Conf. Ser. 38 (2006) 216-219.

DOI: 10.1088/1742-6596/38/1/052

Google Scholar

[7] J. J. Yeh, J. Hwang, K. Bertness, D. J. Friedman, R. Cao, I. Lindau, Growth of the room temperature Au/Si(111)-7×7 interface, Phys. Rev. Lett. 70 (1993) 3768-3771.

DOI: 10.1103/physrevlett.70.3768

Google Scholar

[8] C. J. Choi, Y. W. Ok, T. Y. Seong, H. D. Lee, Effects of a SiO2 Capping Layer on the Electrical Properties and Morphology of Nickel Silicides, Jpn. J. Appl. Phys. 41 (2002) 1969-(1973).

DOI: 10.1143/jjap.41.1969

Google Scholar

[9] F. L. Via, A. Alberti, V. Raineri, S. Ravesi, E. Rimini, Thermal stability of thin CoSi2 layers on polysilicon implanted with As, BF2, and Si, J. Vac. Sci. Technol. B. 16 (1998) 1129-1136.

DOI: 10.1016/s0167-9317(97)00149-4

Google Scholar