[1]
Mark J. Rodwell, C. Y. Huang, Sanghoon Lee, Varistha Chobpattana, Brian Thibeault, William Mitchell, Susanne Stemmer, and Arthur Gossard, Record performance InGaAs MOSFETS targeting ITRS high performance and low-power logic,, ECS Transactions, vol. 66, no. 4, p.135–140, May (2015).
DOI: 10.1149/06604.0135ecst
Google Scholar
[2]
G. Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, N. Mukherjee, and M. Radosavljevic, III-V field-effect transistors for future ultra-low-power applications,, in Proceedings of the Symposium on VLSI Technology (VLSIT), Honolulu, Hawaii, USA, 12-14 June 2012, p.45–46.
DOI: 10.1109/vlsit.2012.6242453
Google Scholar
[3]
J. J. Gu, X. W. Wang, J. Shao, A. T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye, III-V gate-all-around nanowire MOSFET process technology: from 3D to 4D,, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 10-13 Dec. 2012, p.23.7.1-23.7.4.
DOI: 10.1109/iedm.2012.6479091
Google Scholar
[4]
M. Passlack, Off-state current limits of narrow bandgap MOSFETs,, IEEE Transactions on Electron Devices, vol. 53, no. 11, p.2773–2778, Nov. (2006).
DOI: 10.1109/ted.2006.883680
Google Scholar
[5]
K. C. Yu, M. L. Fan, P. Su, and C. T. Chuang, Evaluation of monolithic 3-D logic circuits and 6T SRAMs with InGaAs-n/Ge-p ultra-thin body MOSFETs,, IEEE Journal of the Electron Devices Society, vol. 4, no. 2, p.76–82, March (2016).
DOI: 10.1109/jeds.2016.2524567
Google Scholar
[6]
K. Ganapathi, Y. Yoon, and S. Salahuddin, Analysis of InAs vertical and lateral band-to-band tunneling transistors: leveraging vertical tunneling for improved performance,, Applied Physics Letters, vol. 97, no. 3, Article ID. 033504, July (2010).
DOI: 10.1063/1.3466908
Google Scholar
[7]
Krishna K. Bhuwalka, Zhenhua Wu, Hyeon-Kyun Noh, Wonsok Lee, Mirco Cantoro, Yeon C. Heo, Seonghoon Jin, Woosung Choi, Uihui Kwon, Shigenobu Maeda, Keun H. Lee, and Young K. Park, In0.53Ga0.47As-based nMOSFET design for low standby power applications,, IEEE Transactions on Electron Devices, vol. 62, no. 9, p.2816–2823, Sep. (2015).
DOI: 10.1109/ted.2015.2445977
Google Scholar
[8]
G. Naveen Balaji, S. Chenthur Pandian, and D. Rajesh, Fast test pattern generator using ATALANTA M 2.0,, Asian Journal of Research in Social Sciences and Humanities, vol. 7, no. 2, pp.721-729, Feb. (2017).
DOI: 10.5958/2249-7315.2017.00124.1
Google Scholar
[9]
Naveenbalaji Gowthaman and Viranjay M. Srivastava, Analysis of n-type double-gate MOSFET (at nanometer-scale) using high-K dielectrics for high-speed applications,, 44th Int. Spring Seminar on Electronics Technology (ISSE_G01/P007), Dresden, Germany, 5-7 May (2021).
DOI: 10.1109/isse51996.2021.9467619
Google Scholar
[10]
Viranjay M. Srivastava, Scaling effect on parameters of HfO2 based CSDG MOSFET,, International Journal of Engineering and Technology (IJET), vol. 9, no. 2, pp.420-426, April-May (2017).
DOI: 10.21817/ijet/2017/v9i1/170902322
Google Scholar
[11]
H. Kinoshita, N. Kise, A. Yukimachi, T. Kanazawa, and Y. Miyamoto, Operation of 16-nm InGaAs channel multi-gate MOSFETs with regrown source/drain,, 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), Toyama, Japan, 26-30 June 2016, pp.1-2,.
DOI: 10.1109/iciprm.2016.7528830
Google Scholar
[12]
Mikael Egard, Lars Ohlsson, Mats Ärlelid, Karl-Magnus Persson, Mattias Borg, Filip Lenrick, Reine Wallenberg, Erik Lind, and Lars E. Wernersso, High-frequency performance of self-aligned gate last surface channel In0.53Ga0.47As MOSFET,, IEEE Electron Device Letters, vol. 33, no. 3, p.369– 371, Feb. (2012).
DOI: 10.1109/led.2011.2181323
Google Scholar
[13]
Mandisi Shunqukela and Viranjay M. Srivastava, Dielectric material (HfO2) effect on the surface potential for CSDG MOSFET,, 8th IEEE Int. Conf. on Computer Communication and Informatics (ICCCI), India, 4-6 Jan. 2018, pp.135-139.
DOI: 10.1109/iccci.2018.8441369
Google Scholar
[14]
R. ArunSekar, G. Naveen Balaji, A. Gautami, and B. Sivasankari, High Efficient Carry Skip Adder in various Multiplier Structures,, Advances in Natural and Applied Sciences, vol. 10, no. 14, pp.193-197, Oct. (2016).
Google Scholar
[15]
G. Naveen Balaji, V. Aathira, K. Ambhikavathi, S. Geethiga, and R. Havin, Combinational circuits using transmission gate logic for power optimization,, International Research Journal of Engineering and Technology, vol. 3, no. 5, pp.649-654, May (2016).
DOI: 10.5958/2249-7315.2017.00123.x
Google Scholar