Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs

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Abstract:

In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energy are confirmed.

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Materials Science Forum (Volume 1004)

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837-842

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July 2020

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© 2020 Trans Tech Publications Ltd. All Rights Reserved

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[1] S. Harada, Y. Kobayashi, K. Ariyoshi, T. Kojima, J. Senzaki, Y. Tanaka, and H. Okumura, 3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field, IEEE Electron Devices Letters, 2016, pp.314-316.

DOI: 10.1109/led.2016.2520464

Google Scholar

[2] M. D. Kelley, B. N. Pushpakaran, and S. B. Bayne, Single-Pulse Avalanche Mode Robustness of Commercial 1200 V/80 mΩ SiC MOSFETs, IEEE Transactions on Power Electronics, 2017, pp.6405-6415.

DOI: 10.1109/tpel.2016.2621099

Google Scholar

[3] R. Siemieniec, D. Peters, R. Esteve, et al, A SiC Trench MOSFET concept offering improved channel mobility and high reliability, 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), Warsaw, (2017).

DOI: 10.23919/epe17ecceeurope.2017.8098928

Google Scholar

[4] I. Dchar, M. Zolkos, C. Buttay, H. Morel, Robustness of SiC MOSFET under avalanche conditions, 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, (2017).

DOI: 10.1109/apec.2017.7931015

Google Scholar

[5] A. Kumar, S. Parashar, J. Baliga, and S. Bhattacharya, 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), Investigation of Maximum Junction Temperature for 4H-SiC MOSFET During Unclamped Inductive Switching Test, San Antonio, (2018).

DOI: 10.1109/apec.2018.8341404

Google Scholar

[6] Y. Nanen, M. Aketa, H. Asahara, T. Nakamura, Estimation of junction temperature at failure of SiC DMOSFETs in UIS test, 2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Kyoto, (2016).

DOI: 10.1109/imfedk.2016.7521700

Google Scholar

[7] D. Peters, R. Siemieniec, T. Aichinger, T. Basler, R. Esteve, W. Bergner, Performance and ruggedness of 1200V SiC — Trench — MOSFET, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, (2017).

DOI: 10.23919/ispsd.2017.7988904

Google Scholar

[8] A. Fayyaz, A. Castellazzi, G. Romano, M. Riccio, A. Irace, J. Urresti, and N. Wright, UIS failure mechanism of SiC power MOSFETs, 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, (2016).

DOI: 10.1109/wipda.2016.7799921

Google Scholar

[9] X. Zhou, H. Su, R. Yue, G. Dai, J. Li, et al, A Deep Insight Into the Degradation of 1.2-kV 4H-SiC mosfets Under Repetitive Unclamped Inductive Switching Stresses, IEEE Transactions on Power Electronics, 2018, pp.5251-5261.

DOI: 10.1109/tpel.2017.2730259

Google Scholar

[10] A. Fayyaz, A. Castellazzi, G. Romano, M. Riccio, A. Irace, J. Urresti, N. Wright, Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, (2017).

DOI: 10.23919/ispsd.2017.7988986

Google Scholar