SiC MOSFET with a Self-Aligned Channel Defined by Shallow Source-JFET Implantation: A Simulation Study

Tomasz Sledziewski; Tobias Erlbacher

doi:10.4028/www.scientific.net/MSF.1004.850

Paper Titles

Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs
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Experimental Analysis of 600V 4H-SiC Vertical and Lateral MOSFETs Fabricated on the same 6-Inch Substrate Using a Single Process
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Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs
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Influence of Aluminum Compensation Effects in 4H-SiC on the Performance of VDMOS Transistors
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SiC MOSFET with a Self-Aligned Channel Defined by Shallow Source-JFET Implantation: A Simulation Study
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Improved SiC MOSFET SPICE Model to Avoid Convergence Errors
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Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs
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1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop
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Common-Drain Bidirectional 1200V SiC MOSFETs
p.882

HomeMaterials Science ForumMaterials Science Forum Vol. 1004SiC MOSFET with a Self-Aligned Channel Defined by...

SiC MOSFET with a Self-Aligned Channel Defined by Shallow Source-JFET Implantation: A Simulation Study

Abstract:

A new concept for SiC MOSFET with a self-aligned channel is presented. The channel is defined by shallow source-JFET implantation into a counter-doped layer. This concept is verified by TCAD device simulations. It is shown that the method is applicable to fabrication of functional devices. The most critical parameter of the process is misalignment between channel and p-shield. Almost no change of electrical current in forward conduction state and the leakage current and electric field in the gate oxide in blocking state is observed for the misalignments below 400 nm.