Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress

Jia Xing Wei; Si Yang Liu; Sheng Li; Li Zhi Tang; Rong Cheng Lou; Hao Fu; Hang Bo Zhao; Wei Feng Sun; Xiao Bing Zhang; Song Bai

doi:10.4028/www.scientific.net/MSF.1004.998

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HomeMaterials Science ForumMaterials Science Forum Vol. 1004Investigations on the Resistance Reduction Effect...

Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress

Abstract:

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (R_dson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E_⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.

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Periodical:

Materials Science Forum (Volume 1004)

Pages:

998-1003

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.1004.998

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Online since:

July 2020

Authors:

Jia Xing Wei, Si Yang Liu, Sheng Li, Li Zhi Tang, Rong Cheng Lou, Hao Fu, Hang Bo Zhao, Wei Feng Sun*, Xiao Bing Zhang, Song Bai

Keywords:

Double-Trench, Repetitive Avalanche Stress, Resistance Reduction Effect, SiC-MOSFET

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