Paper Titles

Outlook for Dielectric/SiC Interfaces for Future Generation MOSFETs
p.93

Passivation of Very Fast Near-Interface Traps at the 4H-SiC/SiO₂ Interface Using Sodium Enhanced Oxidation
p.101

Influence of Post-Ion-Implantation Annealing Temperature on the Characteristics of Gate Oxide on 4H Silicon Carbide
p.107

Evolution of Interface State Density and Near Interface Oxide Traps under Controlled Nitric Oxide Annealing in SiO₂/SiC Lateral MOSFETs
p.113

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations
p.119

The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability
p.127

NO Annealing Simulation of 4H-SiC/SiO₂ by Charge-Transfer Type Molecular Dynamics
p.135

Improvement of Interface Properties for Thermally Oxidized SiC/SiO₂ MOS Capacitor by Post Oxidation Annealing Treatment
p.141

High Mobility Silicon Dioxide Layers on 4H-SiC Deposited by Means of Atomic Layer Deposition
p.147

HomeMaterials Science ForumMaterials Science Forum Vol. 1090Oxide and Interface Defect Analysis of lateral...

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

Article Preview

Abstract:

We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.

By email View Pdf

You might also be interested in these eBooks

International Conference on Silicon Carbide and Related Materials ICSCRM 2022

Silicon Carbide MOSFETs and Special Materials

Info:

Periodical:

Materials Science Forum (Volume 1090)

Pages:

119-126

DOI:

https://doi.org/10.4028/p-k93y93

Citation:

Cite this paper

Online since:

May 2023

Authors:

Aleksandr Vasilev*, Maximilian Wolfgang Feil, Christian Schleich, Bernhard Stampfer, Gerhard Rzepa, Gregor Pobegen, Tibor Grasser, Michael Waltl

Keywords:

4H-SiC, Border Traps, Hysteresis, Interface Traps, MOSFETs, Non-Radiative Multi-Phonon Model, TCAD Modeling

Export:

RIS, BibTeX

Permissions:

Creative Commons CC BY 4.0

Share:

Citation:

* - Corresponding Author

[1] B. J. Baliga, "Trends in Power Semiconductor Devices", IEEE Transactions on Electron Devices, Vol. 43, no. 10, pp.1717-1731 (1996)

DOI: 10.1109/16.536818

[2] R. Singh, "Reliability and performance limitations in SiC power devices", Microelectronics Reliability, Vol. 46, no. 5-6, pp.713-730 (2006)

DOI: 10.1016/j.microrel.2005.10.013

[3] C. Yang, Z. Gu, Z. Yin, F. Qin and D. Wang, "Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress", Journal of Physics D: Applied Physics, Vol. 52, no. 40, p.405103 (2019)

DOI: 10.1088/1361-6463/ab2faf

[4] E. X. Zhang, C. X. Zhang, D. M. Fleetwood, R. D. Schrimpf, S. Dhar, S.-H. Ryu, X. Shen, and S. T. Pantelides, "Bias-Temperature Instabilities in 4H-SiC Metal-Oxide-Semiconductor Capacitors", IEEE Transactions on Device and Materials Reliability, Vol. 12, no. 2, pp.391-398 (2012)

DOI: 10.1109/tdmr.2012.2188404

[5] Q. J. Sun, Y. M. Zhang, Q. W. Song, X. Y. Tang, Y. M. Zhang, C. Z. Li, and Y. M Zhang, "Near-interface oxide traps in 4H-SiC MOS structures fabricated with and without annealing in NO", Chinese Physics B, Vol. 26, no. 12, p.127701 (2017)

DOI: 10.1088/1674-1056/26/12/127701

[6] H. Yoshioka, T. Nakamura, and T. Kimoto, "Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance", Journal of Applied Physics, Vol. 111, no. 1, p.014502 (2012)

DOI: 10.1063/1.3673572

[7] A. Chanthaphan, T. Hosoi, S. Mitani, Y. Nakano, T. Nakamura, T. Shimura, and H. Watanabe, "Investigation of unusual mobile ion effects in thermally grown SiO2 on 4H-SiC(0001) at high temperatures", Applied Physics Letters, Vol. 100, p.252103 (2012)

DOI: 10.1063/1.4729780

[8] H. A. Moghadam, S. Dimitrijev, J. Han, and D. Haasmann, "Active defects in MOS devices on 4H-SiC: A critical review", Microelectronics Reliability, Vol. 60, pp.1-9 (2016)

DOI: 10.1016/j.microrel.2016.02.006

[9] R. Arora, J. Rozen, D. M. Fleetwood, K. F. Galloway, C. X. Zhang, J. Han, S. Dimitrijev, F. Kong, L. C. Feldman, S. T. Pantelides, and R. D. Schrimpf, "Charge Trapping Properties of 3C- and 4H-SiC MOS Capacitors With Nitrided Gate Oxides", IEEE Transactions on Nuclear Science, Vol. 56, no. 6, pp.3185-3191 (2009)

DOI: 10.1109/tns.2009.2031604

[10] Y. Fujino, and K, Kita, "Estimation of near-interface oxide trap density at SiO2/SiC metal-oxidesemiconductor interfaces by transient capacitance measurements at various temperatures", Journal of Applied Physics, Vol. 120, no. 8, p.085710 (2016)

DOI: 10.1063/1.4961871

[11] X.-M. Chen, B.-B. Shi, X. Li, H.-Y. Fan, C.-Z. Li, X.-C. Deng, H.-H. Luo, Y.-D. Wu, and B. Zhang, "Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs", Chinese Physical Society and IOP Publishing, Vol. 30, no. 4, p.048504 (2021)

DOI: 10.1088/1674-1056/abd391

[12] P. Fiorenza, F. Iucolano, M. Saggio, and F. Roccaforte, "Oxide Traps Probed by Transient Capacitance Measurements on Lateral SiO2/4H-SiC MOSFETs", Materials Science Forum, Vol. 924, pp.285-288 (2018)

DOI: 10.4028/www.scientific.net/msf.924.285

[13] G. Y. Chung, C. C. Tin, J. H. Won, J. R. Williams, K. McDonald, R. A. Weller, and L. C. Feldman, "Interface state densities near the conduction band edge in n-type 4H-and 6H-SiC", IEEE Aerospace Conference, Vol. 5, pp.409-413 (2000)[14] D. Peters, T. Aichinger, T. Basler, G. Rescher, K. Puschkarsky, H. Reisinger, "Investigation of threshold voltage stability of SiC MOSFETs", 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp.40-43 (2018)

DOI: 10.1109/ispsd.2018.8393597

[15] Y. J. He, X. Y. Tang, Y. F. Jia, C. Q. Zhou, and Y. M. Zhang, "Temperature-dependent effect of near-interface traps on SiC MOS capacitance", Chinese Physics Letters, Vol. 35, no. 10, p.107301 (2018)

DOI: 10.1088/0256-307x/35/10/107301

[16] I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio,and S. Daliento, "SiC MOSFET C-V Curves Analysis with Floating Drain Configuration", Materials Science Forum, Vol. 1062, pp.663-668 (2022)

DOI: 10.4028/p-96q66n

[17] L. Maresca, I. Matacena, M. Riccio, A. Irace, G. Breglio, and S. Daliento, "Influence of the SiC/SiO2 SiC MOSFET interface traps distribution on C-V measurements evaluated by TCAD simulations", IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 9, no. 2, pp.2171-2179 (2021)

DOI: 10.1109/jestpe.2019.2940143

[18] Y. Cai, H. Xu, P. Sun, Z. Zhao and Z. Chen, "Influence of the Interface Traps Distribution on IV and CV Characteristics of SiC MOSFET Evaluated by TCAD Simulations", IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), pp.398-402 (2021)

DOI: 10.1109/wipdaasia51810.2021.9656084

[19] L. Maresca, I. Matacena, M. Riccio, A. Irace, G. Breglio, and S. Daliento, "TCAD model calibration for the SiC/SiO2 interface trap distribution of a planar SiC MOSFET", IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), pp.1-5 (2020)

DOI: 10.1109/wipdaasia49671.2020.9360298

[20] https://www.globaltcad.com/. Accessed on: August 24 (2022)

[21] T. Grasser, "Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities", Microelectronics Reliability, Vol. 52, no. 1, pp.39-70 (2012)

DOI: 10.1016/j.microrel.2011.09.002

[22] C. Schleich, J. Berens, G. Rzepa, G. Pobegen, G. Rescher, S. Tyaginov, T. Grasser, M. Waltl, "Physical Modeling of Bias Temperature Instabilities in SiC MOSFETs", 2019 IEEE International Electron Devices Meeting (IEDM), p.20.5.1-20.5.4 (2019)

DOI: 10.1109/iedm19573.2019.8993446

[23] S. E. Tyaginov, M. Jech, G. Rzepa, A. Grill, A.-M. El-Sayed, G. Pobegen, A. Makarov, T. Grasser, "Border Trap Based Modeling of SiC Transistor Transfer Characteristics", 2018 International Integrated Reliability Workshop (IIRW), Oct. 2018, pp.1-5 (2018)

DOI: 10.1109/iirw.2018.8727083

[24] K. Fukuda, J. Hattori, H. Asai, M. Shimizu, and T. Hashizume, "Simulation of GaN MOS capacitance with frequency dispersion and hysteresis", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.233-236 (2017)

DOI: 10.23919/sispad.2017.8085307

[25] N. Shiono and C. Hashimoto, "Threshold-Voltage Instability of n-Channel MOSFET's under Bias-Temperature Aging", IEEE Transactions on Electron Devices, Vol. 29, no. 3, pp.361-368 (1982)

DOI: 10.1109/t-ed.1982.20710