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High-Temperature Adhesive Bonding of 4H-SiC Substrates
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SmartSiC™ 150 & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

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Abstract:

The Smart Cut™ technology enables the integration of high-quality SiC layer transfers, thereby optimizing device yield. It employs low resistivity handle wafers (below 5 mOhm.cm) to minimize conduction and switching losses for both 150mm and 200mm wafers. Material characterization indicates potential RDSon reductions of up to 15% or 30% for advanced 1200V SiC MOSFETs and JFETs. A 24% RDSon improvement for 650V SiC MOSFETs has been demonstrated, with potential reductions of up to 30% for next-generations 1200V SiC MOSFETs. Proton irradiation which is inherent to the SmartCut™ technology induces an increased ruggedness with regards to bipolar degradation. Additionally, the polycrystalline SiC used as the main material for the die has shown to double power cycling lifetime in silver sintering die attachment An increase of 20K of the maximum junction temperature could be applied without compromising the reliability of the die attach , allowing for a further current increase of up to 10%.

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Periodical:

Materials Science Forum (Volume 1156)

Pages:

65-74

DOI:

https://doi.org/10.4028/p-7vQ6Zj

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Online since:

September 2025

Authors:

Eric Guiot*, Gonzalo Picun, Frédéric Allibert, Alexis Drouin, Walter Schwarzenbach

Keywords:

Bipolar Degradation, Low Resistivity, Power Cycling, SiC Layer Transfer, SiC MOSFETs, SmartCutTM, SmartSiCTM, Specific on Resistance

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Creative Commons CC BY 4.0

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* - Corresponding Author

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