High-Temperature Performance of 1200 V, 200 A 4H-SiC Power DMOSFETs

Lin Cheng; Sei Hyung Ryu; Anant K. Agarwal; Michael  J. O'Loughlin; Albert A. Burk; Jim Richmond; Aivars J. Lelis; Charles Scozzie; John W. Palmour

doi:10.4028/www.scientific.net/MSF.717-720.1065

Paper Titles

A Novel 4H-SiC Fault Isolation Device with Improved Trade-Off between On-State Voltage Drop and Short Circuit SOA
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Fabrication Issues of 4H-SiC Static Induction Transistors
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High Performance SiC IEMOSFET/SBD Module
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Development of 1200 V, 3.7 mΩ-cm² 4H-SiC DMOSFETs for Advanced Power Applications
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High-Temperature Performance of 1200 V, 200 A 4H-SiC Power DMOSFETs
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690V, 1.00 mΩcm² 4H-SiC Double-Trench MOSFETs
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SiC MOSFET Reliability Update
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Material Defects and Rugged Electrical Power Switching in Semiconductors
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Comparative Study of SiC MOSFETs in High Voltage Switching Operation
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HomeMaterials Science ForumMaterials Science Forum Vols. 717-720High-Temperature Performance of 1200 V, 200 A...

High-Temperature Performance of 1200 V, 200 A 4H-SiC Power DMOSFETs

Abstract:

We have investigated the thermal behavior of our recently developed 1200 V, 200 A 4H-SiC power DMOSFETs operating from 20°C up to 300°C. Compared to the first generation SiC DMOSFET that was commercially released early this year, this 4H-SiC power DMOSFET shows a ~ 50% reduction in the total specific on-resistance at room temperature. Temperature dependence of the key parameters of this MOSFET, such as on-resistance, threshold voltage, and the MOS channel mobility, are reported in this paper. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependence of the total on-resistance in different temperature regimes has been observed.

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Periodical:

Materials Science Forum (Volumes 717-720)

Pages:

1065-1068

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.717-720.1065

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Online since:

May 2012

Authors:

Lin Cheng, Sei Hyung Ryu, Anant K. Agarwal, Michael J. O'Loughlin, Albert A. Burk, Jim Richmond, Aivars J. Lelis, Charles Scozzie, John W. Palmour

Keywords:

High-Temperature, Interface Trap, Inversion Layer Electron Mobility, MOS Channel Mobility, Power DMOSFET

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References

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