Complementary JFET Logic for Low-Power Applications in Extreme Environments

H. Habib; N.G. Wright; A.B. Horsfall

doi:10.4028/www.scientific.net/MSF.740-742.1052

Paper Titles

Insulating Properties of Package for Ultrahigh-Voltage, High-Temperature Devices
p.1036

Power Module Package Structure Capable of Surviving Greater ΔTj Thermal Cycles
p.1040

Electromagnetic Interference in Silicon Carbide DC-DC Converters
p.1044

4H-SiC Digital Logic Circuitry Based on P+ Implanted Isolation Walls MESFET Technology
p.1048

Complementary JFET Logic for Low-Power Applications in Extreme Environments
p.1052

PWM Power Supply Using SiC RESURF JFETs with High Speed Switching
p.1056

High-Speed Drive Circuit with Separate Source Terminal for 600 V / 40 A Normally-off SiC-JFET
p.1060

High Temperature Digital and Analogue Integrated Circuits in Silicon Carbide
p.1065

Vertical Channel Silicon Carbide JFETs Based Operational Amplifiers
p.1069

HomeMaterials Science ForumMaterials Science Forum Vols. 740-742Complementary JFET Logic for Low-Power...

Complementary JFET Logic for Low-Power Applications in Extreme Environments

Abstract:

The static and dynamic characteristics of Complementary JFET (CJFET) logic inverter are studied across a range of temperatures and supply voltages to assess potential improvements in performance of digital logic functions for operation in extreme environments. The logic inverter is truly the core of all digital designs. The design and analysis of inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. At 500 deg C and operating at a supply voltage of 1 V, the CJFET inverter have noise margin comparable to that of room temperature silicon and silicon on insulator CMOS inverters. Furthermore, the static power dissipation by CJFET inverter at 500 deg C is 20.6 nW which is six orders of magnitude lower than that by current SiC technologies, making CJFET technology ideal for achieving complex logic functions, far greater than a few-transistors ICs, in the nearer term.

You might also be interested in these eBooks

Silicon Carbide and Related Materials 2012

View Preview

Info:

Periodical:

Materials Science Forum (Volumes 740-742)

Pages:

1052-1055

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.740-742.1052

Citation:

Cite this paper

Online since:

January 2013

Authors:

H. Habib, N.G. Wright, A.B. Horsfall

Keywords:

Enhancement Mode, High-Temperature, Logic Inverter, Noise Margin, Propagation Delay, Silicon Carbide (SiC), Static Power Dissipation

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] P. G. Neudeck, et al., Electrochemical Society Transactions, 41 (2011) 163-176.

Google Scholar

[2] H. Habib, et al., Advanced Materials Research 413 (2012) 391-398.

Google Scholar

[3] H. Habib, et al., Advanced Materials Research 413 (2012) 229-234.

Google Scholar

[4] Y. Goldberg, et al., Properties of Advanced Semiconductor Materials, Wiley, (2001).

Google Scholar

[5] J. P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publisher, (2001).

Google Scholar

[6] H. Ramakrishnan, Strained Silicon Technology for Low-Power High-Speed Circuit Applications, Newcastle University, Newcastle upon Tyne (2008), 93-131.

Google Scholar

[7] E. Sicard and S. B. Dhia, Advanced CMOS cell design, McGraw-Hill, (2007).

Google Scholar