Simulation of TEDREC Phenomena for 4H-SiC Pin Diode with p/n Type Drift Layer

Koji Nakayama; Tetsuro Hemmi; Katsunori Asano

doi:10.4028/www.scientific.net/MSF.740-742.1107

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HomeMaterials Science ForumMaterials Science Forum Vols. 740-742Simulation of TEDREC Phenomena for 4H-SiC Pin...

Simulation of TEDREC Phenomena for 4H-SiC Pin Diode with p/n Type Drift Layer

Abstract:

Temperature dependence simulations of forward characteristics for 4H-SiC pin diodes with Shockley-type stacking faults are performed in order to investigate the mechanism of the TEDREC phenomena. The forward voltage drops of both n-type and p-type drift layers at room temperature increase as the length of the Shockley-type stacking fault increases. When the diodes are compared to each other at the same temperature, the differences between the forward voltage drops do not change significantly up to 150 oC, but the differences suddenly narrow in the range from 150 °C to 200 °C. The Shockley-type stacking fault prevents current from flowing at room temperature. The current, however, flows throughout the drifted diode when the temperature is raised.

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Periodical:

Materials Science Forum (Volumes 740-742)

Pages:

1107-1110

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.740-742.1107

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Online since:

January 2013

Authors:

Koji Nakayama, Tetsuro Hemmi, Katsunori Asano

Keywords:

4H-SiC, N-Type Drift Layer, PiN Diode, P-Type Drift Layer, Shockley-Type Stacking Fault, TEDREC

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