Materials Science Forum Vols. 740-742

Abstract: Our group has developed a novel abrasive-free planarization technique known as catalyst-referred etching (CARE). It can produce flat, undamaged, and smooth SiC surfaces with a root-mean-square roughness of less than 0.1 nm over a whole wafer. This study investigates the etching mechanism of CARE by performing X-ray photoelectron spectroscopy (XPS) measurements to determine the termination species of CARE-processed SiC surfaces. We compared XPS spectra of a CARE-processed surface with those of an as-received SiC surface that had been treated with 50% HF solution. XPS spectra of the CARE-processed wafer contain the F 1s core level, whereas those of an as-received SiC wafer surface did not. This indicates that F anions play an important role in the etching process of CARE.

Abstract: Plasma-assisted polishing (PAP) was successfully applied to single-crystal SiC to obtain an atomically flat surface without introducing any scratches. To clarify the flattening mechanism and increase the material removal rate (MRR) of PAP, investigation of the oxidation process in PAP is essential. In this study, we observed 4H-SiC (0001) surfaces processed by water vapor plasma oxidation using angle resolved X-ray photoelectron spectroscopy (ARXPS). Water vapor plasma oxidation was conducted for 1 min and 5 min. SiO2 and silicon oxycarbide were observed as the oxidation products. A decrease in the plasma irradiation time decreased the thickness of the oxide layer, particularly that of the silicon oxycarbide layer.

Abstract: In this work we investigate the effect of the aluminum p-well implant annealing process on the electrical properties of lateral 4H-SiC MOSFET transistors. The interface trap concentration was measured by quasi-static capacitive voltage (QSCV) and negative bias stress measurements on MOSFETs. We found that higher annealing temperatures significantly reduce the trap density in the lower bandgap, and as a consequence the threshold voltage drift of the transistor after negative stress is reduced.

Abstract: Effect of a shallow nitrogen implantation in the channel region of n-channel 4H-SiC Hall bar MOSFETs on their electrical properties has been characterized by Hall effect. A significant improvement of Hall mobility in normally-off devices is observed with increasing nitrogen implantation dose up to 10¹³ cm^-2 with a peak Hall mobility of 42.4 cm².V^-1.s^-1. Coulomb scattering as dominant scattering mechanism up to room temperature is demonstrated using temperature dependent MOS-Hall effect characterization.

Abstract: We study the structure of SiC/SiO₂ interface defects and the effects of negative bias temperature stress (NBTS) in lateral 4H silicon carbide (SiC) PMOSFETs. Our devices have 90 nm thick SiO₂ gate oxides thermally grown in N₂O ambient at 1280°C on n-type SiC. We investigate virgin (unstressed) and stressed devices using two different techniques: (i) for electrical characterization, we use the direct-current current-voltage (DCIV) technique [1] which measures a recombination current via interface defects and charge pumping (CP) which measures the number of interface defects within a certain range of the SiC band gap; (ii) to study the structure of the defects, we use electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) [2]. The elevated temperature during NBTS is provided by in-situ heated test structures. This is the first EDMR study of p-doped SiC MOSFETs and the first negative bias temperature instability (NBTI) study of SiC MOSFETs using in-situ (on-chip) heating during stress.

Abstract: 4H-SiC n-channel lateral MOSFETs were manufactured and characterized electrically by current-voltage measurements and by numerical simulation. To describe the observed electrical characteristics of the SiC MOSFETs, Near-Interface Traps (NIT) and mobility degradation models were included in the simulation. The main finding of the simulation is that two models for the NIT states in the upper part of the SiC bandgap are able to describe the electrical data equally well. In one of them, acceptor-like traps and fixed charge are considered while in a newly developed one, donor-like traps are taken into account also.

Abstract: To study mobility limiting mechanisms in (0001) 4H-SiC, lateral n-channel MOSFETs in p-implanted wells on n-type epitaxial layers were manufactured and additionally selectively shallow implanted with different nitrogen (N) doses in the channel region. The mobility was found to be limited by Columbic scattering at low electric fields. Further surface roughness scattering was con-sidered as a possible mobility degradation mechanism at high electric fields. First investigations of the SiC surface by atomic force microscopy (AFM) in the channel region after implantation, anneal-ing, and gate oxide removal revealed a rather rough topology. This could lead to fluctuations in the surface potential at the SiC/SiO2 interface, thus accounting in part for surface roughness scattering.

Abstract: 4H-SiC MOSFETs were characterized using charge pumping (CP) technique to monitor interface state density (D_it) not only in the upper half of the bandgap (E_g) but also in the lower half of E_g. Comparison between POCl₃- and NO-annealed MOSFETs was made using CP technique to reveal the different interface properties. The CP measurements of MOSFETs revealed that POCl₃ annealing can reduce D_it near E_c, whereas it increases donor-like D_it in the lower half of E_g.

Abstract: Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for power electronics applications. We have found that SiC MOSFETs when gate-biased at 150 °C show an increasing charge pumping current over time, suggesting that interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above linear-with-log-time and mimics previously observed threshold voltage instabilities, though a causal relationship has not yet been determined. We found the charge trapping after 10⁴ s of BTS increased at a rate of 1x10¹¹ cm^-2/dec for NBTS (-3 MV/cm), 0.7x10¹¹ cm^-2/dec for PBTS (3 MV/cm), and 0.3x10¹¹ cm^-2/dec when grounded. The observed increase in charge trapping has negative implications for the long term stability and reliability of SiC MOS devices under operating conditions.

Abstract: Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.