Interface Defects and Negative Bias Temperature Instabilities in 4H-SiC PMOSFETs – A Combined DCIV/SDR Study

Thomas Aichinger; Patrick M. Lenahan; Dethard Peters

doi:10.4028/www.scientific.net/MSF.740-742.529

Paper Titles

Study of Terminated Species on 4H-SiC (0001) Surfaces Planarized by Catalyst-Referred Etching
p.510

XPS Analysis of 4H-SiC Surfaces Oxidized by Helium-Based Atmospheric-Pressure Water Vapor Plasma for Plasma-Assisted Polishing
p.514

Electrical Impact of the Aluminum P-Implant Annealing on Lateral MOSFET Transistors on 4H-SiC N-Epi
p.521

Hall Effect Characterization of 4H-SiC MOSFETs: Influence of Nitrogen Channel Implantation
p.525

Interface Defects and Negative Bias Temperature Instabilities in 4H-SiC PMOSFETs – A Combined DCIV/SDR Study
p.529

Verification of Near-Interface Traps Models by Electrical Measurements on 4H-SiC n-Channel Mosfets
p.533

Correlation of Interface Characteristics to Electron Mobility in Channel-Implanted 4H-SiC Mosfets
p.537

Characterization of POCl₃-Annealed 4H-Sic Mosfets by Charge Pumping Technique
p.541

Evaluation of PBTS and NBTS in SiC MOS Using In Situ Charge Pumping Measurements
p.545

HomeMaterials Science ForumMaterials Science Forum Vols. 740-742Interface Defects and Negative Bias Temperature...

Interface Defects and Negative Bias Temperature Instabilities in 4H-SiC PMOSFETs – A Combined DCIV/SDR Study

Abstract:

We study the structure of SiC/SiO₂ interface defects and the effects of negative bias temperature stress (NBTS) in lateral 4H silicon carbide (SiC) PMOSFETs. Our devices have 90 nm thick SiO₂ gate oxides thermally grown in N₂O ambient at 1280°C on n-type SiC. We investigate virgin (unstressed) and stressed devices using two different techniques: (i) for electrical characterization, we use the direct-current current-voltage (DCIV) technique [1] which measures a recombination current via interface defects and charge pumping (CP) which measures the number of interface defects within a certain range of the SiC band gap; (ii) to study the structure of the defects, we use electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) [2]. The elevated temperature during NBTS is provided by in-situ heated test structures. This is the first EDMR study of p-doped SiC MOSFETs and the first negative bias temperature instability (NBTI) study of SiC MOSFETs using in-situ (on-chip) heating during stress.

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Materials Science Forum (Volumes 740-742)

Pages:

529-532

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.740-742.529

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Online since:

January 2013

Authors:

Thomas Aichinger, Patrick M. Lenahan, Dethard Peters

Keywords:

Electrically Detected Magnetic Resonance, MOSFET, Negative Bias Temperature Instability, Polyheater, Polysilicon Heater, Silicon Carbide (SiC)

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