Materials Science Forum Vols. 821-823

Abstract: Studies in the literature have shown how the different processing steps can have an impact on the electronic properties of SiC devices. In this contribution, we will review the importance of preserving the crystalline integrity of SiC epilayers through the major processing steps like etching, implantation and oxidation. It will be shown that the major cause for SiC device failures, e.g bipolar degradation and low field effect mobility, is the presence of carbon-related defects like the carbon vacancy (V_C) and carbon interstitials (C_i). At last, the different techniques devised to reduce the presence of these harmful defects will also be reviewed.

Abstract: Basal plane dislocations (BPDs) introduced into SiC epitaxial layers, 25 μm thick, by the combination of implantation and activation anneal are directly observed by ultraviolet photoluminescence (UVPL) imaging. BPD loops appear to originate at micron-sized or smaller areas at the surface. These loops expand by gliding along the basal plane in the offcut direction until the loops approach the substrate. The loops can glide perpendicular to the offcut direction by many millimeters.

Abstract: Image quality (IQ) values of an electron-back-scattering diffraction (EBSD) pattern were used to investigate layer recrystallization for the phosphorus-implanted 4H SiC. We prepared a slope-structured amorphous Si on a Si substrate sample to simulate the recrystallization model of the ion-implanted layer after activation annealing. Phosphorus-implanted and recrystallize-annealed Si and SiC samples were also investigated and the Kikuchi-pattern obscuration was observed for a thicker a-Si layer on the slope-structured sample. The IQ values also decreased. Our results show that ion-implantation damage recovery can be estimated by the EBSD pattern analysis. IQ value variation is in good agreement with the sheet resistance changing with the annealing temperature. The IQ values obtained from the EBSD measurements can be used for crystalline recovery estimation on impurity-implanted SiC layer in a nanoscale resolution.

Abstract: This work has focused on using a deposited SiO₂ layer as the surface protection for 3C-SiC post-implantation activation annealing process. The 3C-SiC epilayers are grown on a Si substrate, nitrogen implanted and then annealed. Both physical and electrical characterisation tools are used to evaluate the influential factors, including implantation doses, semiconductor surface roughness and post-implantation anneal conditions. It is found out that, the SiO₂ capped samples achieved lower specific contact resistance in highest temperature conditions. The lowest contact resistivity of the SiO₂ capped sample is 4.9x10^-6Ω.cm², which is 65.4% lower than the unprotected sample annealed in the same condition.

Abstract: P-type 4H-SiC layers have been obtained by different 400°C Al+ ion implantation processes of semi insulating 4H-SiC wafers and identical 1950°C/5 min post implantation annealing. Implanted Al+ concentration have been 4.7×1018, 9.3×1018, and 4.7×1019 cm-3, thickness of the implanted layer about 630 nm. Electrical characterizations have been performed in the temperature range 100 – 580 K. With decreasing temperature, the onset of a hole conduction through an impurity band has been seen for all the specimens.

Abstract: Shallow and deep levels in SiC significantly affect dynamic characteristics of SiC devices; larger ionization energy and/or a smaller capture cross-section of levels in the SiC bandgap lead to a larger emission time constant and slower response of carriers. Nevertheless, knowledge about those levels is very limited. In this study, we clarified the ionization energy and the capture cross section of the Al shallow acceptor in 4H-SiC in a wide range of doping concentration by preparing appropriate samples and measuring them by thermal admittance spectroscopy. Furthermore, high densities of deep levels were discovered in Al⁺-implanted samples, which can degrade 4H-SiC device performance without any care.

Abstract: We investigated the relationship between secondary defects and electrical characteristics in the activation annealing (1600 °C-1800 °C) of 4H-SiC after Al implantation (3 × 10¹⁷ cm^-3-3 × 10¹⁹ cm^-3). X-ray topography revealed that the dislocation density did not increase after implantation and annealing. Scanning transmission electron microscopy (STEM) images revealed black spots that aggregate with increase in Al dose. The results of energy dispersive X-ray spectroscopy analysis suggested that these black spots are due to the strain of secondary defects. The I-V characteristics at reverse bias of a pin diode fabricated with Al implantation show that secondary defects shown as black spots in the STEM images do not affect the electrical characteristics under the implantation and annealing conditions used in this experiment.

Abstract: Heavily doped layers were formed in 4H-SiC device epitaxial structures comprised of moderately doped n layer (channel) and heavily doped p⁺ layer (gate). The n⁺ regions were formed by local ion implantation of nitrogen followed by post-implantation annealing with graphite capping layer. It was shown that annealing at 1700 °C is required for complete activation of implanted impurities. The post-implantation anneals were found to have no significant effect on the moderately nitrogen doped channel layer. On the other hand it resulted in noticeable deterioration of electrical propertied of heavily doped epitaxial p⁺ layers leading to the increase of contact resistivity which has to be taken into account in design and processing of SiC devices.

Abstract: The knowledge of the Hall factor is essential to convert Hall to drift transport data, in order to fit them and reliably evaluate doping and compensation levels of samples. By introducing empirical mass anisotropy factors, reasons were given in favour of a generalized use of the unique experimental evaluation of the Hall factor reported by the literature for p-type 4H-SiC, which has been assessed for an Al acceptor density in the range of 1.8×10¹⁵ - 2×10¹⁸ cm^-3. Using such a curve, carrier transport data, taken in Al⁺ implanted 4H-SiC for an Al concentration of 5×10¹⁹ cm^-3 after either 2000°C/30s microwave annealing or 1950°C/300s conventional annealing, were analysed through a standard relaxation time approximation model. A slight difference was evidenced in the compensation level of the samples, also resulting in a different ionization energy of the acceptor.

Abstract: Ohmic contacts with low contact resistance, smooth surface morphology, and a well-defined edge profile are essential to ensure optimal device performance. Ohmic contacts often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O₂ rich ambient at temperatures of 800 °C or less, affecting the specific contact resistivity (ρ_C) and RMS surface roughness. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOSFET structures. In order to prevent damage during the high-κ formation, a passivation layer capable of protecting the contacts during annealing is required. In this work we have investigated the suitability of PECVD silicon nitride as a passivation layer to protect Ohmic contacts during high temperature, oxygen rich annealing.