Materials Science Forum Vols. 821-823

Abstract: The mixed gas of nitrogen and hydrogen was used for the plasma nitridation of SiC surface.A small amount of hydrogen was effective to activate the nitridation reaction and suppress the oxidationreaction. The interface properties were improved by using nitride layer as an interfacial bufferlayer of SiC MIS structure.

Abstract: The effect of the alternative nitridation process of the 4H-SiC/SiO₂ interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated. C-V and G-V measurements on inversion-channel MOS devices revealed similar results to the conventional N₂O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.

Abstract: We report on the electrical characterization of the Metal-Oxide-Semiconductor (MOS) interfacerealized on in-situ Ge-doped n-type 4H-SiC epilayers grown by Chemical Vapour Deposition(CVD). In order to study the relevance of this novel material for MOSFET technology, and in particularwhether the Ge presence deteriorates the SiC/SiO2 interface, we investigated the electrical propertiesof MOS capacitors realized on this novel substrate. Capacitance-Voltage measurements, performedto determine the quality of the SiC/SiO2 interface, show that the interface traps concentration is notincreased by the Ge content. The current through the oxide layer, monitored to study the bulk oxidequality and the tunneling mechanisms, indicates that Fowler-Nordheim conduction occurs and that thesubstrate-to-oxide barrier for electrons is comparable to the reported values for the SiC/SiO2 system.

Abstract: Charge trapping behavior in Al₂O₃/SiC MOS structures was investigated by C-V hysteresis measurements in combination with XPS analysis. According to the quadratic fit of C-V hysteresis vs. t_ox curves, the density of the injected charges in the bulk Al₂O₃ films are the same under different maximum electric field, while the density of sheet charges increase with the increase of maximum electric field. Thus, a simple sheet charge model has been used to evaluate the actual effect of the electron injection phenomenon. The charge trapping levels can be as high as 10¹³ cm^-2, indicating the importance of C-V hysteresis in Al₂O₃/SiC structures. All the trapping charges are found to be located at a distance ranging from 3 to 4 nm from the interface. Furthermore, no detectable interface oxide between Al₂O₃ and SiC has been found through our XPS measurements. We conclude that the origin of charge trapping sites in Al₂O₃/SiC structures is the native defects in ALD Al₂O₃ layer and predominantly the border traps in the Al₂O₃ near the oxide/semiconductor interface.

Abstract: Mechanical blade dicing is a state-of-the-art technique for the chip separation of SiC devices. Due to the hardness of SiC this technique suffers from low feed rate and high wear of the diamond coated dicing blade, resulting in the risk of uncontrolled tool breakage during the dicing process. With the upcoming transition to 150 mm diameter of SiC wafers this technique will most probably reach its limit. For dicing SiC wafers of those diameters on a productive scale three alternative dicing technologies are considered in this paper: ablation laser dicing, Stealth Dicing and Thermal Laser Separation. All these methods are based on laser processing. The benefits of these technologies are discussed in detail and compared to the classical mechanical diamond blade dicing, including a brief summary of first experimental results on each of the three laser dicing technologies.

Abstract: A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) are demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss can be negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

Abstract: One challenge for volume manufacturing of 4H-SiC devices is the state-of-the-art wafer dicing technology – the mechanical blade dicing which suffers from high tool wear and low feed rates. In this paper we discuss Thermal Laser Separation (TLS) as a novel dicing technology for large scale production of SiC devices. We compare the latest TLS experimental data resulting from fully processed 4H-SiC wafers with results obtained by mechanical dicing technology. Especially typical product relevant features like process control monitoring (PCM) structures and backside metallization, quality of diced SiC-devices as well as productivity are considered. It could be shown that with feed rates up to two orders of magnitude higher than state-of-the-art, no tool wear and high quality of diced chips, TLS has a very promising potential to fulfill the demands of volume manufacturing of 4H-SiC devices.

Abstract: Effects of ICP power and pressure on microtrenching, striation, roughness and sidewall angles in SF₆ based ICP-RIE etching of SiC have been studied. The results show that ICP RIE etching parameters such as ICP power and pressure can effect both striation and microtrenches and these challenges could be eliminated by optimizing etching parameters.

Abstract: Catalyst-referred etching (CARE) is a planarization method based on the chemical etching reaction, which does not need abrasives. In this paper, CARE was applied to the planarization of 6-inch silicon carbide (SiC) wafers, and removal properties were investigated. The etching rate was about 20nm/h, which is almost equal to that of 2-inch SiC wafer (16 nm/h). The rms roughness was reduced along with the removal depth, and step-terrace structure was observed in whole area of the on-axis wafer surface.

Abstract: To remove the surface damages induced during mechanical polishing (MP) of 4H-SiC, a variety of wet etching recipes and etching conditions were studied. By evaluating the epilayers grown on these etching-treated wafers, it has been found that triangular defects (TRDs) are the main defects originated from the MP-induced damages in these samples. High temperature molten KCl etching at 1100 °C with KOH additive is very effective to remove the damaged surface while keeping a relatively flat surface. Epilayer grown on the KCl+KOH etched wafer showed a TRD density <0.9 cm^-2.