Materials Science Forum Vols. 821-823

Abstract: A systematic study on the 3C-SiC/SiO₂ interface has been done. 3C-SiC epilayers have been grown on a Si (001) substrate. Results obtained from room temperature conductance-voltage (G-V) and hi-low capacitance-voltage (C-V) on n-type 3C-SiC/SiO₂ metal-oxide-semiconductor capacitors (MOS-Cs) have been reported using various types of oxides. The oxides used in these studies have been thermally grown at different oxidation temperatures - 1200°C, 1300°C and 1400°C. Also, the interface trap density (D_it) of as-grown MOS-C is compared with nitrided (thermally grown oxide + N₂O post-oxidation annealing) oxides. Oxide grown at 1300°C followed by N₂O-passivation at the same temperature gives the lowest D_it of 6x10¹¹ cm^-2eV^-1 at 0.2eV from the conduction band (CB) edge.

Abstract: The mechanism of dielectric breakdown of oxide on step-bunching of 4H-silicon carbide (SiC) was investigated. Comparing the surface morphology obtained before forming metal-oxide-semiconductor (MOS) capacitor and optical emission on the capacitor under electrical stress, it was cleared that current concentrates on step-bunching and it often caused preferential dielectric breakdown. Based on TEM analysis and the observation of time dependence of emission under the stress, a new model was proposed to explain the dielectric breakdown on step-bunching.

Abstract: This work reports about influence of step bunching of SiC epitaxial-wafer surface on Fowler-Nordheim (F-N) tunneling emission current of SiC-MOS capacitor. We have measured the effective barrier height (Φ_B) of SiO₂/SiC interface, and estimated the deterioration factor of the effective Φ_B on step bunching surface by calculating the local tunneling emission currents. Step bunching fluctuates the gate oxide thickness. The effective Φ_B value can be successively derived using our proposed partitioned model in which constant Φ_B value of flat surface is used. The fluctuation of the oxide film thickness results in the convergence of F-N tunneling emission currents at the thinner oxide in the MOS capacitor.

Abstract: Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

Abstract: Electrical properties of the gate oxides thermally grown in N₂O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

Abstract: A high-temperature process is used to enhance the CO_x desorption rate to reduce trap density in SiC/SiO₂ interface for SiC MOSFETs. Interface state density as measured by Terman method and C-ψs method for the oxidation processes at a high temperature of 1350°C show significant improvement compared to traditional Si thermal oxidation temperature of 1200°C. The higher oxidation temperature led to a much faster growth rate and some observable hysteresis in the CV curves, which could be due to electron trap and can be resolved by NO_x post oxidation anneal (POA).

Abstract: In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO₂ and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with ¹²C, ¹⁴N and ²⁸Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO₂ as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of D_its due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.

Abstract: We present the influence of phosphorous auto-doping on the characteristics of the oxide interface in 4H-SiC following high temperature gate oxide annealing. IV characteristics show no evidence of direct tunnelling breakdown; however Fowler Nordheim (F-N) conduction is observed in high electric field with the oxides able to sustain >10MV/cm. Capacitance Voltage data show D_IT <1x10¹² eV^-1cm^-2 close to the conduction band edge after POA, with undoped samples demonstrating D_IT below 5x10¹¹ eV^-1cm^-2. Photo CV data indicates smaller flat band voltage shifts of 0.6V at midpoint for the undoped samples, in comparison to 0.9V for the phosphorous doped devices. Temperature and bias stress tests at 200°C showed marginal hysteresis (0.3V) in both wafers. Reliability of time-dependent constant current and constant voltage characteristics revealed higher TDDB lifetimes in the undoped wafer. We conclude that the unintentional incorporation of phosphorous into the gate stack as a result of high temperature POA of the doped field oxide leads to a variation in flat band shift, higher D_IT, and lower dielectric reliability.

Abstract: This paper describes the effects of phosphorus implantation into n-type 4H-SiC substrate prior to standard dry oxidation process. Phosphorus incorporation has been reported to be one of the most efficient means of increasing SiC MOSFET field mobility however the physical basis of this phenomenon is still not clear. The aim of this research is to investigate the influence of phosphorus implantation on trap density profile close to conduction band of silicon carbide and to gain understanding of physical processes responsible for observed trap density improvement in phosphorus related oxidation technologies of silicon carbide.

Abstract: MOS capacitors have been fabricated on (0001), (11-20) and (000-1) oriented 4H-SiC under different post-oxidation anneal (POA) conditions. 100 MHz conductance measurement shows the generation of very fast donor-type interface traps after NO anneal for both Si-face (0001) and a-face (11-20), but not on C-face (000-1). Fast traps were not observed in POCl₃ annealed samples for any orientation. Smallest D_it (at 0.2 eV below conduction band edge) was obtained on Si-face using POCl₃ anneal (1.4x10¹¹ cm^-2 eV^-1), on a-face using NO anneal (2.5x10¹¹ cm^-2 eV^-1) and on C-face using POCl₃ anneal (4.5x10¹² cm^-2 eV^-1).