Influence of Phosphorous Auto-Doping on the Characteristics of SiO2/SiC Gate Dielectrics

Ming Hung Weng; A.E. Murphy; Craig Ryan; B.J.D. Furnival; Dave A. Smith; David T. Clark; R.A.R. Young; Ewan P. Ramsay; Robin. F. Thompson; A.B. Horsfall

doi:10.4028/www.scientific.net/MSF.821-823.492

Paper Titles

Influence of Annealing, Oxidation and Doping on Conduction-Band near Interface Traps in 4H-SiC Characterized by Low Temperature Conductance Measurements
p.476

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO₂ Interfaces
p.480

Improving Interface Quality of 4H-SiC MOS Devices with High Temperature Oxidation Process in Mass Produce Furnace
p.484

Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation
p.488

Influence of Phosphorous Auto-Doping on the Characteristics of SiO₂/SiC Gate Dielectrics
p.492

Influence of Phosphorus Implantation on Electrical Properties of Al/SiO₂/4H-SiC MOS Structure
p.496

Characteristics of MOS Capacitors with NO and POCl₃ Annealed Gate Oxides on (0001), (11-20) and (000-1) 4H-SiC
p.500

Plasma Nitridation of 4H-SiC by Glow Discharge of N₂/H₂ Mixed Gases
p.504

Passivation of 4H-SiC/SiO₂ Interface Traps by Oxidation of a Thin Silicon Nitride Layer
p.508

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Influence of Phosphorous Auto-Doping on the Characteristics of SiO₂/SiC Gate Dielectrics

Abstract:

We present the influence of phosphorous auto-doping on the characteristics of the oxide interface in 4H-SiC following high temperature gate oxide annealing. IV characteristics show no evidence of direct tunnelling breakdown; however Fowler Nordheim (F-N) conduction is observed in high electric field with the oxides able to sustain >10MV/cm. Capacitance Voltage data show D_IT <1x10¹² eV^-1cm^-2 close to the conduction band edge after POA, with undoped samples demonstrating D_IT below 5x10¹¹ eV^-1cm^-2. Photo CV data indicates smaller flat band voltage shifts of 0.6V at midpoint for the undoped samples, in comparison to 0.9V for the phosphorous doped devices. Temperature and bias stress tests at 200°C showed marginal hysteresis (0.3V) in both wafers. Reliability of time-dependent constant current and constant voltage characteristics revealed higher TDDB lifetimes in the undoped wafer. We conclude that the unintentional incorporation of phosphorous into the gate stack as a result of high temperature POA of the doped field oxide leads to a variation in flat band shift, higher D_IT, and lower dielectric reliability.