Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation

Sethu Saveda Suvanam; David M. Martin; Carl Mikael Zetterling; Anders Hallén

doi:10.4028/www.scientific.net/MSF.821-823.488

Paper Titles

Evaluation of F-N Tunneling Emission Current in MOS Capacitor Fabricated on Step Bunching
p.472

Influence of Annealing, Oxidation and Doping on Conduction-Band near Interface Traps in 4H-SiC Characterized by Low Temperature Conductance Measurements
p.476

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO₂ Interfaces
p.480

Improving Interface Quality of 4H-SiC MOS Devices with High Temperature Oxidation Process in Mass Produce Furnace
p.484

Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation
p.488

Influence of Phosphorous Auto-Doping on the Characteristics of SiO₂/SiC Gate Dielectrics
p.492

Influence of Phosphorus Implantation on Electrical Properties of Al/SiO₂/4H-SiC MOS Structure
p.496

Characteristics of MOS Capacitors with NO and POCl₃ Annealed Gate Oxides on (0001), (11-20) and (000-1) 4H-SiC
p.500

Plasma Nitridation of 4H-SiC by Glow Discharge of N₂/H₂ Mixed Gases
p.504

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Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation

Abstract:

In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO₂ and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with ¹²C, ¹⁴N and ²⁸Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO₂ as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of D_its due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.