Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

David J. Spry; Philip G. Neudeck; Liang Yu Chen; Laura J. Evans; Dorothy Lukco; Carl W. Chang; Glenn M. Beheim

doi:10.4028/www.scientific.net/MSF.858.1112

Paper Titles

Cascode Configuration of SiC-BGSIT and Si-MOSFET with Low On-Resistance and High Transconductance
p.1095

Newly Developed Switching Analysis Method for 3.3 kV 400 a Full SiC Module
p.1099

Novel vs Conventional Bipolar Logic Circuit Topologies in 4H-SiC
p.1103

3D Integration of Si-Based Peltier Device onto 4H-SiC Power Device
p.1107

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect
p.1112

Atomistic Simulations and Interfacial Morphology of Graphene Grown on SiC(0001) and SiC(000-1) Substrates
p.1121

The Interaction between Graphene and the SiC Substrate: Ab Initio Calculations for Polar and Nonpolar Surfaces
p.1125

Interfacial Disorder of Graphene Grown at High Temperatures on 4H-SiC(000-1)
p.1129

Wafer-Scale Graphene on 4-Inch SiC
p.1133

HomeMaterials Science ForumMaterials Science Forum Vol. 858Evidence of Processing Non-Idealities in 4H-SiC...

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

Abstract:

The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.