Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices

Ming Hung Weng; Muhammad I. Idris; H.K. Chan; A.E. Murphy; D.A. Smith; D.T. Clark; R.A.R. Young; E.P. Ramsay; Alton B. Horsfall

doi:10.4028/www.scientific.net/MSF.858.631

Paper Titles

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors
p.615

Microscopic Difference between Dry and Wet Oxidations of C-Face 4H-SiC MOSFFETs Studied by Electrically Detected Magnetic Resonance
p.619

High Temperature Nitridation of 4H-SiC MOSFETs
p.623

Improvement of SiO₂/4H-SiC Interface Quality by Post-Oxidation Annealing in N₂ at High-Temperatures
p.627

Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices
p.631

Effect of Activation Annealing and Reactive Ion Etching on MOS Channel Properties of (11-20) Oriented 4H-SiC
p.635

Systematic Investigation of 4H-SiC Trench Properties Dependence on Channel Concentration, Crystallographic Plane, and MOS Interface Treatment
p.639

Influence of Oxide Processing on the Defects at the SiC-SiO₂ Interface Measured by Electrically Detected Magnetic Resonance
p.643

Investigation of the Interface Quality and Reliability of 4H-SiC MOS Structure with NO and Forming Gas Annealing Treatment
p.647

HomeMaterials Science ForumMaterials Science Forum Vol. 858Analytical Evaluation of Thermally Oxidized and...

Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices

Abstract:

We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×10¹² cm^-2eV^-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm^-1. The channel mobility extracted from n-and pMOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm²V^-1s^-1, which are limited by the high doping level in the epilayers used in this study.