The Influence of Temperature Storage on Threshold Voltage Stability for SiC VDMOSFET

Abstract:

Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆V_TH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.

• Periodical: Materials Science Forum (Volume 954)
• Pages: 144-150
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.954.144
• Online since: May 2019
• Authors: Zhi Qiang Bai, Xiao Yan Tang, Chao Han*, Yan Jing He, Qing Wen Song, Yi Fan Jia, Yi Men Zhang, Yu Ming Zhang
• Keywords: 4H-SiC MOSFET, Gate-Bias Stress, Temperature Storage, Threshold Voltage Stability

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