An Optimized p+ Shielding 4H-SiC Trench Gate MOSFETs Structure with Floating Regions

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In this paper, an optimized p+ shielding 4H-SiC trench-gate metal-oxide-semiconductor field effect transistors (UMOSFETs) structure with floating regions is proposed. The p+ shielding region is moved down to gain a low device on-resistance and the floating regions are designed to improve the breakdown voltage in the proposed structure. Specific on-resistances of the proposed 4H-SiC UMOSFETs is 2.62 mΩ.cm2 at VGS=18 V and VDS=10 V, compared with 4.77 mΩ.cm2 for the conventional p+ shielding UMOSFETs structure with same breakdown voltage. The on-resistance and figure of merit (FOM = VBR2/Ron) improve by 45.1% and 94.2%, respectively.

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157-162

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May 2019

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© 2019 Trans Tech Publications Ltd. All Rights Reserved

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[1] B.J. Baliga, Silicon Carbide Power Devices, World Scientific Publishing Co. Pte. Ltd. (2005).

Google Scholar

[2] J. A. Cooper and A. Agarwal, SiC power-switching devices—the second electronics revolution? Proc. IEEE, vol. 90 (2002) 956-968.

DOI: 10.1109/jproc.2002.1021561

Google Scholar

[3] Y.Li, J.A. Cooper and M.A. Capano, High Voltage (3 kV) UMOSFETs in 4H-SiC, IEEE Trans. Electron Devices, vol.49 (2002) 972-975.

DOI: 10.1109/ted.2002.1003714

Google Scholar

[4] J.A. Cooper, Jr., Structure for Increasing the Maximum Voltage of Silicon Carbide UMOS Power Transistors, U.S. Patent 6,180,958 (2001).

Google Scholar

[5] Y. Sui, T. Tsuji and J. A. Cooper, Jr, On-State Characteristics of SiC Power UMOSFETs on 115-um Drift Layers, IEEE Electron Device Lett., vol. 26 (2005) 255-257.

DOI: 10.1109/led.2005.845495

Google Scholar

[6] Yasuhiro Kagawa , Nobuo Fujiwara, Katsutoshi Sugawara, Rina Tanaka, Yutaka Fukui, Yasuki Yamamoto, Naruhisa Miura, Masayuki Imaizumi, Shuhei Nakata and Satoshi Yamakawa, 4H-SiC trench MOSFET with bottom oxide protection, Mat. Sci. Forum, vol. 778-780 (2014) 919-922.

DOI: 10.4028/www.scientific.net/msf.778-780.919

Google Scholar

[7] S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, and H. Okumura, Determination of optimum structure of 4H-SiC trench MOSFET, in Proc. ISPSD, Bruges, Belgium, Jun. 1-5 (2012).

DOI: 10.1109/ispsd.2012.6229071

Google Scholar

[8] S. Harada, Y. Kobayashi, K. Ariyoshi, T. Kojima, J. Senzaki, Y. Tanaka and H. Okumura, 3.3kV-class 4H-SiC MeV-implanted UMOSFET with reduced gate oxide field, IEEE Electron Device Lett., vol. 37 (2016) 314-316.

DOI: 10.1109/led.2016.2520464

Google Scholar

[9] A. K. Agarwal, J. B. Casady. L. B. Rowland, W. F. Valck, M. H.White and C. D. Brandt, 1.1 kV 4H-SiC Power UMOSFET's, IEEE Electron Device Lett., vol. 18 (1997) 586-588.

DOI: 10.1109/55.644079

Google Scholar

[10] H. Linewih, S. Dimitrijev, C. E. Weitzel and H. B. Harrison, Novel SiC accumulation-mode power MOSFET, IEEE Trans. Electron Devices, vol. 48 (2001) 1711-1717.

DOI: 10.1109/16.936693

Google Scholar

[11] ATLAS User's Manual: Device Simulation Software, Version 5.16.3.R, Silvaco Int., Santa Clara, CA, (2010).

Google Scholar

[12] Yuichiro Nanen, Muneharu Kato, Jun Suda and Tsunenobu Kimoto. Effects of Nitridation on 4H-SiC MOSFETs Fabricated on Various Crystal Faces, IEEE Trans. Electron Devices, vol. 60 (2013) 1260-1262.

DOI: 10.1109/ted.2012.2236333

Google Scholar

[13] Dai Okamoto, Hiroshi Yano, Kenji Hirata, Tomoaki Hatayama and Takashi Fuyuki, Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide, IEEE Electron Device Lett., vol. 31 (2010) 710-712.

DOI: 10.1109/led.2010.2047239

Google Scholar

[14] D. Okamoto, H. Yano, K. Hirata, T. Hatayama and T. Fuyuki, Improved inversion channel mobility in 4H-SiC MOSFETs on Si face utilizing phosphorus-doped gate oxide, IEEE Electron Device Lett., vol. 31 (2010) 710-712.

DOI: 10.1109/led.2010.2047239

Google Scholar

[15] V. Tilak, K. Matocha, G. Dunne, F. Allerstam and E. Ö. Sveinbjörnsson, Trap and inversion layer mobility characterization using Hall effect in silicon carbide-based MOSFETs with gate oxides grown by sodium enhanced oxidation, IEEE Trans. Electron Devices, vol. 56 (2009) 162-169.

DOI: 10.1109/ted.2008.2010601

Google Scholar