Implementing an In Situ Surface Preparation Prior to Ni Deposition for Ni Salicide Processes

Kyuh Wan Chang; Scott Bolton; Marc Rossow; Rich Gregory; Jack Jiang; Dharmesh Jawarani; Stefan Zollner; Dean Denning; Jon Cheek

doi:10.4028/www.scientific.net/SSP.134.19

Paper Titles

Etching of Silicon Dioxide with Gas Phase HF and Water: Initiation, Bulk Etching, and Termination.
p.3

Evaluation of the Plasmaless Gaseous Etching Process
p.7

Single Wafer Hydrophobic Surface Preparation on 300mm by HF Vapor
p.11

Insights into HF-Last Processes and Particle Performance in a Single Wafer Spin Cleaning Tool
p.15

Implementing an In Situ Surface Preparation Prior to Ni Deposition for Ni Salicide Processes
p.19

Electrical Impact of Various Arsenic-Residues Cleanings
p.23

Elimination of Watermark on Extremely High-Doped Poly-Silicon Surfaces Using HF-Vapor Cleaning
p.27

Passivation Studies of Germanium Surfaces
p.33

Germanium Surface Passivation Using Ozone Gaseous Phase
p.37

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Implementing an In Situ Surface Preparation Prior to Ni Deposition for Ni Salicide Processes

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Solid State Phenomena (Volume 134)

Pages:

19-22

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.134.19

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Online since:

November 2007

Authors:

Kyuh Wan Chang, Scott Bolton, Marc Rossow, Rich Gregory, Jack Jiang, Dharmesh Jawarani, Stefan Zollner, Dean Denning, Jon Cheek

Keywords:

Nickel Silicide, Phase Transformation, Reactive Preclean, Salicide, Sputter Etch, Surface Preparation, Wafer Cleaning

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References

[1] M. Tinani, et. al., J. Vac. Sci. Technol. B, 19(2), (2001), p.376.

Google Scholar

[2] A. Regnier, et. al., Mater. Sci. Eng. B, Vol. 114-115 (2004), pp.209-213.

Google Scholar

[3] A. H. M. Kamal, et. al., IEEE Trans. Semicon. Manuf., Vol. 15, No. 3, (2002), pp.350-354.

Google Scholar

[4] Y. J. Wu, et. al., IEEE Elec. Dev. Lett., Vol. 20, No. 5 (1999), pp.200-202.

Google Scholar

[5] S. -P. Chung, et. al., Proc. 4th Intern. Symp. on Semicon. Wafer Clean. and Surf. Char., (1998), p.110.

Google Scholar

[6] J. -P. Gonchond, et. al., AIP Conf. Proc., Vol. 788 (2005), pp.182-186.

Google Scholar

[7] C. Lavoie, et. al., Microelectronic Engineering, Vol. 70 (2003), pp.144-157.

Google Scholar