"Damage Free" Cleaning for Advanced BEOL Interconnections

Abstract:

For the 32nm logic technology and beyond, more stringent specifications in terms of dimensions and materials integrity continue to drive the cleaning process improvements. In this paper, post-etch wet cleaning was optimized in order to address CD loss issues and metal hard mask cleaning improvement in a Trench First Hard Mask (TFHM) backend architecture. Based on materials compatibility tests and electrical results, this wet clean process should also be fully compatible with a Via First Trench Last (VFTL) architecture.

• Periodical: Solid State Phenomena (Volume 187)
• Pages: 211-214
• DOI: https://doi.org/10.4028/www.scientific.net/SSP.187.211
• Online since: April 2012
• Authors: Lucile Broussous, Kristell Courouble, Emmanuel Richard, Carole Pernel, Virginie Loup, Didier Lévy
• Keywords: Interconnections Levels, Porous Low-k, Post-Etch Clean

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DOI: 10.7554/elife.31476.005