Fast Estimation of the Lateral Fidelity of Ion Implantation in 4H-SiC through Calibration to JFET Transfer Characteristics in TCAD

Kota Sakai; Norman Boettcher; Maximilian Szabo; Susanne Beuer; Mathias Rommel

doi:10.4028/p-4Rj3jY

Paper Titles

Design of Al₂O₃/LaAlO₃/SiO₂ Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs
p.79

Channel Density Design Guidelines for the Transient Characteristics of SiC Trench Gate MOSFETs
p.89

Analysis of On-State and Short-Circuit Capability in 3D Trench SiC MOSFET Designs
p.97

Revised Channel Mobility Model for Predictive TCAD Simulations of 4H-SiC MOSFETs
p.103

Improvement of Reflectance Spectroscopy for Oxide Layers on 4H-SiC
p.109

Doping and Temperature Dependence of Carrier Lifetime in 4H SiC Epitaxial Layers
p.115

Fail-to-Open Short Circuit Failure Mode of SiC Power MOSFETs: 2-D Thermo-Mechanical Modeling
p.121

Gate Resistance Integration in SiC MOSFETs: Performance Simulations under Different Implementation Methods
p.127

Fast Estimation of the Lateral Fidelity of Ion Implantation in 4H-SiC through Calibration to JFET Transfer Characteristics in TCAD
p.133

HomeSolid State PhenomenaSolid State Phenomena Vol. 358Fast Estimation of the Lateral Fidelity of Ion...

Fast Estimation of the Lateral Fidelity of Ion Implantation in 4H-SiC through Calibration to JFET Transfer Characteristics in TCAD

Abstract:

In the 4H-SiC device fabrication process, ion implantation of aluminium to form p-regions results in spreading (lateral straggling) from the mask design width by a few 100 nm. This has a significant impact on device performance, so device design must take lateral straggling into account. In this study, the impact of lateral straggling is estimated by applying a Gaussian distribution to one dimensional depth profiles obtained from Monte Carlo simulations. In our studies, this approach reduced the computation time by a factor of 300 compared to two-dimensional Monte Carlo simulations. The parameters describing the Gauss function are determined with the aid of fabricated JFET test structures. The pinch-off behaviour of JFET devices with vertical and horizontal channels was analysed in electrical TCAD simulations and calibrated to the characteristics of the fabricated devices. Ultimately, the electrical characteristics of simulations and measurements were found to be in good agreement.

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Periodical:

Solid State Phenomena (Volume 358)

Pages:

133-140

DOI:

https://doi.org/10.4028/p-4Rj3jY

Citation:

Cite this paper

Online since:

August 2024

Authors:

Kota Sakai, Norman Boettcher*, Maximilian Szabo, Susanne Beuer, Mathias Rommel

Keywords:

4H-SiC, Ion Implantation, JFET, Lateral Straggling, Monte Carlo, TCAD

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Creative Commons CC BY 4.0

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* - Corresponding Author

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