Design of Al2O3/LaAlO3/SiO2 Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs

Lin Hua Huang; Yong Liu; Xin Peng; Takashi Tsuji; Yuichi Onozawa; Naoto Fujishima; Johnny Kin On Sin

doi:10.4028/p-9MknRR

Paper Titles

Temperature Dependence of 4H-SiC Gate Oxide Breakdown and C-V Properties from Room Temperature to 500 °C
p.51

Detection of Very Fast Interface Traps at 4H-SiC/AlN and 4H-SiC/Al₂O₃ Interfaces
p.59

A Voltage Adjustable Diode Integrated SiC Trench MOSFET with Barrier Control Gate
p.65

Effects of High Gate Voltage Stress on Threshold Voltage Stability in Planar and Trench SiC Power MOSFETs
p.71

Design of Al₂O₃/LaAlO₃/SiO₂ Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs
p.79

Channel Density Design Guidelines for the Transient Characteristics of SiC Trench Gate MOSFETs
p.89

Analysis of On-State and Short-Circuit Capability in 3D Trench SiC MOSFET Designs
p.97

Revised Channel Mobility Model for Predictive TCAD Simulations of 4H-SiC MOSFETs
p.103

Improvement of Reflectance Spectroscopy for Oxide Layers on 4H-SiC
p.109

HomeSolid State PhenomenaSolid State Phenomena Vol. 358Design of Al2O3/LaAlO3/SiO2 Gate Stack on Various...

Design of Al₂O₃/LaAlO₃/SiO₂ Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs

Abstract:

An Al₂O₃/LaAlO₃/SiO₂ gate stack is designed and implemented on various trench-gate channel planes for high-performance trench power MOSFETs. The designed high-k gate stack achieves a significant enhancement in the gate blocking capability (~1.73X) and maintains a low interface state density (D_it), in comparison to the SiO₂ gate. Moreover, owing to the implementation of the high-k gate stack, the high-k trench gate MOSFETs conduct a drain current of approximately 1.3 times larger than that of the SiO₂ trench gate MOSFETs on all 24 channel planes at the same overdrive voltage (V_gs-V_th) of 10 V. An analysis of the mobility limiting mechanisms on different channel planes reveals that the highest channel mobility on the (1120) channel plane is primarily due to its largest Coulomb scattering mobility and surface roughness scattering mobility.

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Periodical:

Solid State Phenomena (Volume 358)

Pages:

79-87

DOI:

https://doi.org/10.4028/p-9MknRR

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Online since:

August 2024

Authors:

Lin Hua Huang*, Yong Liu, Xin Peng, Takashi Tsuji, Yuichi Onozawa, Naoto Fujishima, Johnny Kin On Sin

Keywords:

Channel Mobility Limiting Mechanisms, Channel Planes, High-k Gate Stack, Interface State Density, SiC Trench Gate Power MOSFETs

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Creative Commons CC BY 4.0

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* - Corresponding Author

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