Temperature Dependence of 4H-SiC Gate Oxide Breakdown and C-V Properties from Room Temperature to 500 °C

Article Preview

Abstract:

Silicon carbide (SiC) is intrinsically more suitable for high temperature operation than silicon. However, for devices and circuits based on metal-oxide-semiconductor, high temperature behavior of gate oxides is still under investigation. This work aims to provide insights on how temperatures from room temperature up to 500 °C affect gate oxide properties of metal-oxide-semiconductor structures. Characterization is performed by current-voltage (I-V) and capacitance-voltage (C-V) measurements with different SiC and polysilicon gate electrode doping types. Increasing breakdown voltages were observed with higher temperatures for n-type SiC doping, while p-type ones break down at lower voltages. Polysilicon doping type only has minor impact on the breakdown voltage but influences the I-V behavior. High temperatures increase the probability of strong inversion being observable in C-V investigation. Regarding the I-V results, it can be stated that the 55 nm gate oxide used in the utilized HT CMOS technology has breakdown voltages above absolute values of around 55 V, independent of any doping types, and no significant current could be observed within the intended 20 V operation range of the technology.

You might also be interested in these eBooks

Info:

* - Corresponding Author

[1] T. Kimoto, J.A. Cooper, Fundamentals of silicon carbide technology: Growth, characterization, devices and applications, Wiley, Singapore, 2014.

Google Scholar

[2] K. Zekentes, K. Vasilevskiy, Advancing Silicon Carbide Electronics Technology I, Materials Research Forum LLC, 2018.

DOI: 10.21741/9781945291852

Google Scholar

[3] M. Herceg, T. Matić, T. Švedek, Comparison of current-voltage characteristics for hypothetic Si and SiC bipolar junction transistor, Elektrotehniski Vestnik/Electrotechnical Review 75 (2008).

Google Scholar

[4] L. Yu, K. P. Cheung, J. Campbell, J. S. Suehle, K. Sheng, Oxide Reliability of SiC MOS Devices, in: 2008 IEEE International Integrated Reliability Workshop Final Report, 2008, p.141–144.

DOI: 10.1109/irws.2008.4796106

Google Scholar

[5] M. Le-Huu, H. Schmitt, S. Noll, M. Grieb, F.F. Schrey, A.J. Bauer, L. Frey, H. Ryssel, Investigation of the reliability of 4H–SiC MOS devices for high temperature applications, Microelectronics Reliability 51 (2011) 1346–1350.

DOI: 10.1016/j.microrel.2011.03.015

Google Scholar

[6] M.K. Kim, S. Chae, C.W. Kim, J.-w. Lee, S. Tiwari, A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories, MRS Proc. 997 (2007).

DOI: 10.1557/proc-0997-i03-12

Google Scholar

[7] A. May, M. Rommel, A. Abbasi, T. Erlbacher, Threshold Voltage Adjustment on 4H-SiC MOSFETs Using P-Doped Polysilicon as a Gate Material, KEM 947 (2023) 57–62.

DOI: 10.4028/p-w6bx49

Google Scholar

[8] Information on https://europractice-ic.com/technologies/asics/fraunhofer-iisb/

Google Scholar

[9] E. Efthymiou, P. Rutter, P. Whiteley, A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating, Microelectronics Reliability 58 (2016) 26–32.

DOI: 10.1016/j.microrel.2015.11.021

Google Scholar

[10] Alberto Salinaro, Characterization and Development of the 4H-SiC/SiO2 Interface for Power MOSFET Applications. Doctoral thesis, 2016.

Google Scholar

[11] K. Kubota, Yoshinari Kamakura, Kenji Taniguchi, Yoshiyuki Sugahara, Ryuichi Shimizu, Dielectric breakdown mechanism in thick SiO2 films revisited, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs (2004) 229–232.

DOI: 10.1109/wct.2004.239938

Google Scholar

[12] K. Murakami, M. Rommel, V. Yanev, T. Erlbacher, A.J. Bauer, L. Frey, A highly sensitive evaluation method for the determination of different current conduction mechanisms through dielectric layers, Journal of Applied Physics 110 (2011).

DOI: 10.1063/1.3631088

Google Scholar