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Paper Titles
Complementary Two Dimensional Carrier Profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy
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Temperature Dependence of 4H-SiC Gate Oxide Breakdown and C-V Properties from Room Temperature to 500 °C
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Detection of Very Fast Interface Traps at 4H-SiC/AlN and 4H-SiC/Al2O3 Interfaces
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A Voltage Adjustable Diode Integrated SiC Trench MOSFET with Barrier Control Gate
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Effects of High Gate Voltage Stress on Threshold Voltage Stability in Planar and Trench SiC Power MOSFETs
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Design of Al2O3/LaAlO3/SiO2 Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs
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Channel Density Design Guidelines for the Transient Characteristics of SiC Trench Gate MOSFETs
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Analysis of On-State and Short-Circuit Capability in 3D Trench SiC MOSFET Designs
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Revised Channel Mobility Model for Predictive TCAD Simulations of 4H-SiC MOSFETs
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Effects of High Gate Voltage Stress on Threshold Voltage Stability in Planar and Trench SiC Power MOSFETs

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Abstract:

Gate oxide reliability is a challenge in SiC MOSFETs particularly due to the presence of high electric field in the dielectric during device operation and blocking, and SiC/SiO2 interfaces suffer from a high density of traps and defects that can cause charge trapping and threshold voltage shift. Highly accelerated gate bias testing can be used for testing gate field effects on device reliability/stability, but care must be taken that the high acceleration biases do not invoke failure mechanisms that fall outside of normal device operation conditions. In this work, we attempt to address that aspect of high voltage gate tests in terms of threshold voltage instability and perform a comparative analysis between commercially available planar and trench SiC MOSFETs.

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Periodical:

Solid State Phenomena (Volume 358)

Pages:

71-77

DOI:

https://doi.org/10.4028/p-02nckO

Citation:

Cite this paper

Online since:

August 2024

Authors:

Ayan K. Biswas*, Daniel J. Lichtenwalner, Suman Das, Caleb Isaacson, Satyaki Ganguly, Donald A. Gajewski

Keywords:

Gate Reliability, Planar MOSFET, Threshold Voltage, Trench MOSFET

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Creative Commons CC BY 4.0

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* - Corresponding Author

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