Solid State Phenomena Vol. 358

Abstract: Single Event Gate Rupture (SEGR) is one of the catastrophic failures caused by heavy ions in power MOS devices. In this study, n-type SiC MOS capacitors representing the gate structure generally used in SiC power MOSFETs were used to conduct heavy ion irradiation tests to clarify the SEGR mechanism. The Linear Energy Transfer (LET) dependence of the critical electric field (E_cr) for these capacitors was evaluated with two different oxidation processes in accumulation to confirm whether the oxidation process affects SEGR tolerance. We found that the E_cr value and slopes of the LET dependence for SEGR between DRY samples and DRY + POA samples were approximately consistent. We also simulated SEGR and studied its mechanism. The simulation results suggested that SEGR for SiC MOS capacitors is caused by carriers in electron-hole pairs generated by a heavy ion instead of gate electric field fluctuation.

Abstract: This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.

Abstract: Investigation of the doped areas in 4H-SiC power devices has been done by non-destructive characterization methods. It consists of local surface potential measurements by Kelvin Probe Force Microscopy (KPFM) coupled with scanning electron microscopy (SEM) and µ-Raman spectroscopy. Near-field mappings of the devices’ surface have been realized, allowing us to discern the differently doped areas.

Abstract: New and original medium power multi-terminal SiC monolithic converter architectures are investigated with vertical switching cells based on SiC JBS diodes and VDMOS transistors. 2D TCAD and mixed-mode Sentaurus™ simulations are performed to optimize switching structures as Buck, Boost, H-bridge high-side row chip common drain-type and low-side row chip common source-type. The proper operation in the turn-on and turn-off of each cell is also studied and validated. To fabricate these new monolithic integrated architectures, two main technological bricks have been developed, for vertical insulation and the integration of a top Ni metal via. To achieve the vertical insulation deep trenches are necessary combining dry plasma and wet KOH electrochemical etching through the thick N⁺ substrate.

Abstract: 4H Silicon Carbide multichannel neural interface devices using NPN junctions for channel isolation were fabricated using four different doping structures. Two devices used thicker, lower-doped epitaxial layers, one used thin, highly-doped implanted layers implanted into a N epilayer, and one used thin-highly-doped implanted layers into an N substrate. The devices were characterized in terms of resistance, charge delivery, leakage current through the substrate, and crosstalk between channels. The thickest, lower-doped epitaxial layers performed best, resulting in great isolation and good performance. While the implanted layers showed high charge delivery, their resistance is reduced due to the thin layers and the isolation is particularly poor.

Abstract: Accelerated aging in reliability testing of gate oxides often involves application of high electric fields well above use case conditions. For wide bandgap devices, for example silicon carbide metal-oxide field effect transistors (SiC-MOSFETs), the barrier between SiC and the gate oxide, typically silicon dioxide (SiO2), is rather small and will thus cause large Fowler-Nordheim (FN) currents and an increased charge trapping rate during reliability testing. Thus, to assess the reliability of SiC-MOSFETs, it might prove useful to better understand the high field charging behavior. We fabricated planar and trench MOS-capacitors, using an oxide deposition process and post oxidation anneal that is known to be prone to anode hole injection. Voltage ramps were measured at different constant ramp speeds at 25 °C and at 175 °C. Additionally, we performed constant voltage stress measurements. The measured voltage ramps were fitted with the FN-equation in the low-field range, where no significant charging is expected. Deviation from the fitted equation at high fields is believed to be due to charging of the oxide, which causes a non-homogenous electric field within the gate oxide. We adapt the rate equations from [1] to model and fit the measured IV-curves using an explicit forward approach. Using the model, we can explain the hump in the current observed during constant voltage stress, corresponding to an average of electric field strength of 7.5 MV/cm, typical for time-dependent dielectric breakdown (TDDB) experiments. The model also shows the strong inhomogeneity of the electric field due to anode hole injection during the initial phase of TDDB, which might cause deviations when extrapolating accelerated aging tests to use conditions. We therefore recommend to slowly ramp up the voltage with a slope <100 mV/s before starting the constant voltage stress phase. This allows for the recombination of the trapped holes to catch up with the anode hole injection and keep steady state conditions. The slow slope also allows some electron trapping before the highest hole concentration is reached, to further reduce the electric field inhomogeneity.

Abstract: The suitability of scanning probe methods based on atomic force microscopy (AFM) measurements is explored to investigate with high spatial resolution the elementary cell of 4H-SiC power MOSFETs. The two-dimensional (2D) cross-sectional maps demonstrated a high spatial resolution of about 5 nm using the scanning spreading resistance microscopy (SSRM) capabilities. Furthermore, the scanning capacitance microscopy (SCM) capabilities enabled visualizing the fluctuations of charge carrier concentration across the different parts of the MOSFETs elementary cell.

Abstract: Silicon carbide (SiC) is intrinsically more suitable for high temperature operation than silicon. However, for devices and circuits based on metal-oxide-semiconductor, high temperature behavior of gate oxides is still under investigation. This work aims to provide insights on how temperatures from room temperature up to 500 °C affect gate oxide properties of metal-oxide-semiconductor structures. Characterization is performed by current-voltage (I-V) and capacitance-voltage (C-V) measurements with different SiC and polysilicon gate electrode doping types. Increasing breakdown voltages were observed with higher temperatures for n-type SiC doping, while p-type ones break down at lower voltages. Polysilicon doping type only has minor impact on the breakdown voltage but influences the I-V behavior. High temperatures increase the probability of strong inversion being observable in C-V investigation. Regarding the I-V results, it can be stated that the 55 nm gate oxide used in the utilized HT CMOS technology has breakdown voltages above absolute values of around 55 V, independent of any doping types, and no significant current could be observed within the intended 20 V operation range of the technology.

Abstract: Modest channel carrier mobility in SiC-MOSFETs with NO annealed gate oxides has been the main factor hampering development of low power devices (300 – 650 V). A very fast interface trap, noted as NI, has been suggested to be the main culprit for poor inversion channel carrier mobility. The origin of the NI trap is unknown, but it is likely a property of the SiO₂ and it is enhanced during post nitridation. In this study we show that the NI trap is also detected in 4H-SiC/AlN and 4H-SiC/Al₂O₃ MIS-capacitors. Observations are done using conductance spectroscopy and capacitance voltage measurements at cryogenic temperatures. This strongly suggests that the NI trap is a property of the SiC surface and not the dielectric used to form the SiC/dielectric interface. Furthermore, a scanning transmission electron microscopy (STEM) was performed to confirm that there are no SiO₂ layers or islands present at the 4H-SiC/AlN and 4H-SiC/Al₂O₃ interfaces.