Solid State Phenomena Vol. 360

Abstract: The aim of this work is to investigate the 3^rd quadrant safe operating area (SOA) of different voltage class SiC MOSFETs under surge current conditions depending on the gate-source voltage. The extent to which an applied gate-source voltage can influence the surge current capability was investigated. For 650 V and 1.2 kV voltage class devices, surge current capability was higher with channel-on mode. However, this behavior was vice-versa for 2 kV and 3.3 kV devices. In this investigation, during the surge current event, the gate-source voltage was switched between different values to optimize the resulting voltage drop. This method can reduce power dissipation during a surge current event, especially for high voltage class SiC MOSFETs.

Abstract: GaN power HEMTs enable the design of power electronic systems with highest efficiencies and reduced size. Despite strong advancements in device reliability, charge carrier trapping is still an important challenge. The applied methodology allows to characterize defects that cause the dynamic R_DS,on in GaN power devices at product level with flexibility in duty cycle, number of pulses and mission profile. A pronounced trapping is observed for lateral GaN-on-Si HEMTs with Schottky p-GaN gate structure at low drain bias and long off-state pulses (> 100 ms). The effect is investigated by fast determination of the on-state resistance R_DS,on under different trap capturing conditions: a) different drain bias b) off-state time and number of cycles c) variation of temperature. The trapping and detrapping effects are characterized and the activation energy is extracted from time constants. An elevated on-state resistance was present for up to 3 hours. The threshold voltage modification due to high drain bias does explain the significant R_DS,on increase.

Abstract: In this paper, we propose a novel 1200V SiC MOSFET featuring the embedded junction-controlled-diode (JCD-MOSFET) and demonstrate its static and dynamic characteristics through TCAD simulations. Without sacrificing blocking and conduction performance, the adoption of JCD can effectively reduce knee voltage to 1.7V based on unipolar carrier conduction mode. Due to the reduced peak reverse recovery current and reverse recovery charge, the JCD-MOSFET achieves 30.8% lower turn-on losses than conventional MOSFET. Meanwhile, the fabrication process for the JCD-MOSFET is the same as conventional MOSFET without an extra mask. This proposed JCD-MOSFET prototype shows great potential in target applications in the near future.

Abstract: SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit excellent high-speed switching characteristics. However, the sheet resistance of the p-body region and the contact resistance between the p-body region and source electrode significantly degrade the switching performance. In this study, to clarify the effect of resistance on switching speed, which has not been sufficiently explored before, we used the temperature dependence of sheet and contact resistance and conducted switching tests under different temperature conditions. Furthermore, we created a circuit model that considered body effects and compared the results of the models with the measurements. We were able to reproduce the same temperature and resistance dependences as those exhibited by the experimental results, thus confirming the effectiveness of the model.

Abstract: Ohmic contacts play a major role in the signal transfer between the semiconductor device and the external circuitry. One of the main technological issues to develop high-performance SiC-based devices is the control of metal/SiC contact properties to fabricate low resistance and high stability SiC Ohmic contacts to p-type SiC. This is mostly due to intrinsic SiC characteristics like large work function, low dopant activation for p-type materials and low hole mobility. These limits are even more emphasized in SiC JBS or MPS diodes, where Schottky and Ohmic contacts on the P doped regions embedded in the active area to improve surge ruggedness are usually formed by using the same metallization process. This naturally results either in a high Schottky barrier height in the Schottky contact with consequent increase of the conduction loss at low currents or in a poorly conductive Ohmic contact, leading to reduced IFSM capability. Therefore, the optimization and control of the process parameters like for example the P⁺ doping concentration peak underneath the metallization layer and the annealing process temperatures is crucial to obtain a good Ohmic contact and enhance the device´s robustness against surge current.

Abstract: Button shear tests at different temperatures between different mold compounds and Cu-leadframes have been performed to evaluate the adhesion of mold compounds to the inner surfaces of SiC-power devices. The results at different temperatures show the behavior of different material and layer stack combinations under storage at room temperatures as well as under operating conditions with elevated temperatures, where adhesion and thus the hermeticity of the device against moisture is significantly lowered. It has been shown that different thermomechanical properties of the mold compounds as well as the usage of different adhesion promoter materials have a significant effect on the adhesion properties of the mold compound to the leadframe surface of the SiC power devices, which have direct impact on the ruggedness and lifetime stability. Furthermore, these results have been correlated to thermomechanical simulations of the package architecture of SiC power devices under stress. Different wire bond architectures have been evaluated in simulations with and without die top delamination taken into account, showing that EMC delamination may play a major role in the lifetime stability of SiC power devices under thermomechanical stress like simulated in TCT- , IOL- and PTC-testing.

Abstract: With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.

Abstract: This paper provides an experimental investigation through infrared thermography of the steady-state temperature imbalance arising in parallel SiC MOSFETs. A switched-mode boost power converter based on two arrays of 4 parallel 1.2 kV MOSFETs is selected as a case-study. The analysis aims at proving that a proper device arrangement can minimize the thermal imbalance in the absence of circuit layout optimization.

Abstract: In this paper, the effect of a non-linear dielectric gate stack on the short-circuit performance of a 1.2 kV SiC MOSFET was analyzed through TCAD simulations. Starting from the TCAD model of a commercial 1.2 kV, its standard gate oxide was replaced with a stack formed by oxide and a non‑linear dielectric, characterized by a temperature dependent permittivity. This variation on temperature can be exploited to reduce the current conducted during short-circuit events, lowering the temperature reached through the device by about 30%, without affecting its static and dynamic performance.