Solid State Phenomena Vol. 361

Abstract: In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (V_th) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in V_th and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

Abstract: Device reliability is an important factor in application, especially in the field of electric mobility. In this paper high cycle fatigue power cycling results of SiC devices in baseplate free modules are presented. To minimize testing time, the devices were stressed with load pulses corresponding to a 50 Hz load. The reliability results are the first fatigue results for temperature swings below 30 K for SiC devices. The lifetime in the high cycle fatigue area is limited by solder fatigue for high virtual junction temperatures of 150 °C. In theory, the reliability should increase exponential since the elastic-plastic transition area is reached. The experiment revealed that the lifetime can still be described by the Coffin-Manson approach also in the high cycle fatigue area. It can be observed that the high junction temperatures weaken the stability of the solder layer, so no major lifetime increase can develop. The measured temperature data are additionally corrected by a three-dimensional (3D) simulation to ensure a validity of the results.

Abstract: Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Abstract: The effect of high-temperature electron and proton irradiation on SiC-based device characteristics is being investigated. Industrial integrated 4H-SiC Schottky diodes, each with an n-type base and a blocking voltage of either 600 V, 1200 V, or 1700 V, manufactured by Wolfspeed, are being studied. 0.9 MeV electron and 15 MeV proton irradiation were applied. It has been found that the irradiation resistance of silicon carbide Schottky diodes at high temperatures significantly exceeds their resistance at room temperature. This effect is attributed to the annealing of compensating defects induced by high-temperature irradiation. The parameters of radiation-induced defects are determined using the method of deep level transient spectroscopy (DLTS). Under high-temperature ("hot") irradiation, the spectrum of radiation-induced defects introduced into SiC appears to differ significantly from the spectrum of defects introduced at room temperature. It is suggested that approximately half of the compensation is due to radiation-induced defects formed in the bottom part of the bandgap.

Abstract: In this work, we investigated the impact of crystallographic defects (specifically stacking faults, SFs) on the mechanisms of the current transport in 4H-SiC Schottky contacts. The electrical characteristics were studied under both forward and reverse bias. In particular, while the presence of SFs under the contact did not show a significant impact on the forward characteristics of the Schottky diode, a significant increase in the leakage current occurred under reverse bias in defective diodes. This anomalous behavior can be explained by a space-charge limited current model, consistent with the presence of a trapping state distribution in the 4H-SiC gap. An increase of the reverse bias above 30 V leads to a complete trap filling. The weak temperature-dependence of the leakage current observed at highest voltage suggests that a tunneling of the carriers through the barrier can be also present.

Abstract: We present an early-stage reliability evaluation approach to assess the impact of surface charges in the passivation overcoat (PO) film layers. This is obtained by applying a so-called accelerated wafer-level reverse breakdown voltage stability test in combination with wafer-level static and Van der Pauw measurements. Here, we applied this approach on 4H-SiC merged PiN Schottky diodes with a single-zone junction termination extension fabricated by using different border doses and PO stacks. Accordingly, the correlation between design parameters and the influence of surface charges can be quickly identified, leading to reduced cycle time and enhanced product reliability by optimizing the design of the JTE parameters already in the development phase. This study supports diodes and MOSFETs product manufacturing with an efficient optimization approach to address design and process impacts toward acquiring long-term lifetime demanded in automotive and industrial applications.

Abstract: Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, V_d and stress time dependent model.

Abstract: In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Abstract: Fault protection of AC and DC network using semiconductors requires accurate electrothermal design of active and passive devices to keep power losses low in nominal condition and to sustain high current overload. Using SiC MOSFET for SSPC arises challenges to keep power losses low and to ensure robustness versus abnormal operating condition. Indeed, unpredictable events can dramatically damage the device integrity such as current overload, short-circuit... To overcome those issues, ones are generally carefully design driving system, implementing sensors and fast digital control circuit computing to sense simultaneously current, voltage and temperature, to analyze and detect abnormal operating condition. To reduce the whole detection transmission and reaction chain, we have designed a 1200V ; 30A ; 65mΩ instrumented SiC MOSFET, including both a current mirror and a temperature sensor in the active area of the die. This paper reports for the first-time real-time SiC instrumented MOSFET temperature and current measurement without the need of external sensors nor estimators.