Solid State Phenomena Vol. 361

Abstract: For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Abstract: We have studied the UIS (Unclamped Inductive Switching) ruggedness of SiC MOSFETs in parallel. We show that UIS ruggedness of parallel MOSFETs is a function of the difference in their breakdown voltage (Δ-BVDSS). As expected, for large Δ-BVDSS UIS, ruggedness is dominated by the lower BVDSS transistor. Somewhat unexpectedly, for small enough Δ-BVDSS, UIS ruggedness is better than the sum of its two transistors. Specifically, the energy that parallel transistors of low Δ-BVDSS can sustain depends on the peak current and is 10%-20% higher than the sum of the energies of the individual transistors. We explain the physical mechanism of this effect and extend the concept to the case of more than 2 parallel transistors. These findings are important for the efficient design of power circuits with multiple die in parallel.

Abstract: In this study, we introduce the impact of gamma irradiation on 4H-SiC based transistor-transistor logic (TTL) inverters. These monolithic bipolar inverters have been successfully demonstrated in a broad spectrum of temperature and supply voltage conditions. In this iteration of experiments, attempts made to the processing to increase beta values. The gamma radiation tests from a ⁶⁰Co source were conducted under various operation conditions and measured in-situ under different biasing conditions. The Silicon Carbide Integrated circuits ( SiC ICs) show excellent tolerance properties to gamma radiation up to doses of nearly 1 MRad. Comparable Si BJT-based TTL inverters show considerable degradation already at one order of magnitude lower doses, clearly demonstrating the superior radiation hardness of 4H-SiC ICs.

Abstract: In this work, MeV alpha particles generated from an accelerator are used to study single event breakdown (SEB) in 4H-SiC MOSFET samples, rated at 3.3 kV. The samples are exposed to bursts of alpha particles under reverse bias conditions to investigate the SEB sensitivity to ion energy and reverse bias. The energies of alpha particles are chosen to reach different depths in the drift region of the MOSFET devices, and also to penetrate the whole drift region. Forward and reverse characteristics are measured after each exposure, as long as no failures occur, to ensure that the device performance is maintained. The measurements show that no significant effects are observed on the drain-source leakage current, while minor effects on gate behavior can be seen as a function of accumulated fluence. Furthermore, SEB can only be triggered with a reverse bias larger than, or equal to 3 kV. A standard MOSFET cell with a similar rated voltage is also simulated in Sentaurus TCAD to study these effects, using two different models for the incident ion-induced ionization: the Alpha Particle and the Heavy Ion model. Simulations show that the Alpha Particle model cannot induce any device failures even with a 3.5 kV reverse bias, while it is possible to trigger a failure by the Heavy Ion model, where the ionization can be selected. Carrier plasma and internal electric field distributions of the two models are plotted and compared, showing that device failures triggered by a heavy ion are related to the hole injection at epi-substrate interface, in which linear energy transfer (LET) of the particle plays an important role.

Abstract: Due to the expansion of defects like single Shockley-type Stacking Faults inside the SiC epitaxial drift layer, during high current stress, classical SiC MOSFETs can be victims of the degradation of their electrical characteristics. The introduction of an epitaxial SiC buffer layer between the substrate and the n- drift epilayer, called recombination-enhancing buffer layer, was shown to avoid this degradation. In this paper, TCAD simulations of the electrical behavior of such a commercial SiC MOSFET device with varying buffer layer thickness are studied, indicating only small modifications of the electrical characteristics. These simulations are combined with the characterization of the local electrical properties using an AFM-sMIM technique, allowing to determine the real thickness of the different layers of the device. These measurements highlight an inhomogeneous conductivity in the SiC substrate, being probably compensated by the introduction of the SiC buffer layer.

Abstract: In this study we analyzed the physical mechanisms governing time-dependent dielectric breakdown (TDDB) and we used TDDB physical model of dielectric breakdown, implemented in the defect-centric Ginestra® modeling platform, to deconvolute the intrinsic material properties effects and geometry feature impact on the gate oxide (GOx) and SiC-device breakdown.

Abstract: A 1.2 kV lateral RESURF Schottky diode (TZ-SBD) have been designed from SZ-SBD that can recover from a single-event effect (SEE) in which a heavy ion traverses the device at a linear energy transfer (LET) of 60 MeV·cm²/mg, ESA’s standard. Compared to SZ-SBD, TZ-SBD has an additional split in the N-drift region which is usually used to improve the electric field distribution so its breakdown voltage is improved by 9%. During the single events simulations, the maximum temperature is 919 K with reverse voltage (VR) = 1200 V and LET = 60 MeV·cm²/mg, which is much lower then the SiC melting temperature (3100 K) and the chemically unstable temperature of SiC in the presence of metal (1073 K).

Abstract: The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3^rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (R_DS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (V_TH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative V_TH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the V_TH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while R_DS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Abstract: Silicon Carbide (SiC) enhancement mode MOS electronics offer several benefits for realizing analog, digital and mixed signal electronics, but limitations on gate dielectric reliability has limited the adoption of MOS in high temperature application. In this work, we report GE’s lateral SiC MOSFETs exceeding previously reported temperature capabilities for SiC MOSFETs with experimental results that have shown that >500°C operation of SiC MOSFETS is possible with >400 hours demonstrated at 620°C, and short-term functionality demonstrated to 800°C. The result shows that MOS-based SiC electronics can continue to be a viable choice for circuit implementations at extreme temperatures >600°C.

Abstract: Dynamic on-state resistance has been experimentally observed in all commercially-available SiC MOSFETs studied on the time scale of normal device operation, and can be explained by the presence of dynamic threshold-voltage instability. The magnitude of this dynamic on-state resistance varies from vendor to vendor, but in every case this magnitude generally corresponds to the magnitude of that device’s threshold-voltage instability, as described by standard textbook equations-especially in the case of large threshold-voltage instabilities.