UIS Ruggedness of Parallel 4H-SiC MOSFETs

Philipp Steinmann; Marco Atzeri; In Hwan Ji; Jared Langan; Kevin Myers; Neal Oldham; Jae Hyung Park; Rahul Potera; Caleb Rinderer; Edward van Brunt

doi:10.4028/p-ostN6y

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HomeSolid State PhenomenaSolid State Phenomena Vol. 361UIS Ruggedness of Parallel 4H-SiC MOSFETs

UIS Ruggedness of Parallel 4H-SiC MOSFETs

Abstract:

We have studied the UIS (Unclamped Inductive Switching) ruggedness of SiC MOSFETs in parallel. We show that UIS ruggedness of parallel MOSFETs is a function of the difference in their breakdown voltage (Δ-BVDSS). As expected, for large Δ-BVDSS UIS, ruggedness is dominated by the lower BVDSS transistor. Somewhat unexpectedly, for small enough Δ-BVDSS, UIS ruggedness is better than the sum of its two transistors. Specifically, the energy that parallel transistors of low Δ-BVDSS can sustain depends on the peak current and is 10%-20% higher than the sum of the energies of the individual transistors. We explain the physical mechanism of this effect and extend the concept to the case of more than 2 parallel transistors. These findings are important for the efficient design of power circuits with multiple die in parallel.

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Periodical:

Solid State Phenomena (Volume 361)

Pages:

65-69

DOI:

https://doi.org/10.4028/p-ostN6y

Citation:

Cite this paper

Online since:

August 2024

Authors:

Philipp Steinmann*, Marco Atzeri, In Hwan Ji, Jared Langan, Kevin Myers, Neal Oldham, Jae Hyung Park, Rahul Potera, Caleb Rinderer, Edward van Brunt

Keywords:

4H-SiC MOSFETs, MOSFETs in Parallel, UIS, Unclamped Inductive Switching

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Creative Commons CC BY 4.0

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* - Corresponding Author

References

[1] J. W. Palmour, L. Cheng, V. Pala, E. V. Brunt, D. J. Lichtenwalner, G.-Y. Wang, J. Richmond, M. O'Loughlin, S. Ryu, S. T. Allen, A. A. Burk, and C. Scozzie, "Silicon carbide power MOSFETs: Breakthrough performance from 900V up to 15kV," in 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

DOI: 10.1109/ispsd.2014.6855980

Google Scholar

[2] P. Steinmann, S. Ganguly, B. Hull, K. Lam, D. Lichtenwalner, J.-H. Park, R. Potera, J. Richmond, J. S.-H. Ryu, S. Sabri, C. V. Brackle, E. V. Brunt, and E. Williams, "Improvements to the analytical model to describe UIS events," IEEE Transactions on Electron Devices 69, v7, pp.3848-3853 (2022)

DOI: 10.1109/TED.2022.3174516

Google Scholar

[3] A. Fayyaz, A. Castellazzi, G. Romano, M. Riccio, A. Irace, J. Urresti, and N. Wright, "UIS failure mechanism of SiC power MOSFETs," IEEE 4th Workshop WiPDA (2016)

DOI: 10.1109/WiPDA.2016.7799921

Google Scholar

[4] P. Steinmann, B. Hull, In-Hwan Ji, D. Lichtenwalner, and E. V. Brunt, "Temperature dependence of avalanche breakdown in 4H-SiC," Journal of Applied Physics 133, v. 23, p.235705 (2023)

DOI: 10.1063/5.0152385

Google Scholar