Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

Kwang Won Lee; Jake Choi; Young Ho Seo; Kyeong Seok Park; Martin Domeij; Fredrik Allerstam

doi:10.4028/p-D7iozT

Paper Titles

Dependence of the Silicon Carbide Radiation Resistance on the Irradiation Temperature
p.21

Anomalous Electrical Behavior of 4H-SiC Schottky Diodes in Presence of Stacking Faults
p.27

Early-Stage Reliability Evaluation of Passivation Stack and Termination Designs in SiC MPS Diodes
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A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB
p.39

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure
p.47

Experimental Demonstration of Ultra-Fast SiC MOSFET Overload Protection Using Embedded Current and Temperature Sensors
p.53

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs
p.59

UIS Ruggedness of Parallel 4H-SiC MOSFETs
p.65

The Impact of Gamma Irradiation on 4H-SiC Bipolar Junction Inverters under Various Biasing Conditions
p.71

HomeSolid State PhenomenaSolid State Phenomena Vol. 361Design Optimization and Reliability Evaluation in...

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

Abstract:

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

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Periodical:

Solid State Phenomena (Volume 361)

Pages:

47-52

DOI:

https://doi.org/10.4028/p-D7iozT

Citation:

Cite this paper

Online since:

August 2024

Authors:

Kwang Won Lee*, Jake Choi, Young Ho Seo, Kyeong Seok Park, Martin Domeij, Fredrik Allerstam

Keywords:

4H-SiC Trench MOSFET, Deep P, Gate Oxide Integrity, GOI, Reliability, TDDB

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Creative Commons CC BY 4.0

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* - Corresponding Author

References

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