A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB

Peter Moens; Martin Domeij; Jean Francois Cano; Luc de Schepper; Stefan Verleye; Fredrik Allerstam

doi:10.4028/p-CB1KRz

Paper Titles

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests
p.13

Dependence of the Silicon Carbide Radiation Resistance on the Irradiation Temperature
p.21

Anomalous Electrical Behavior of 4H-SiC Schottky Diodes in Presence of Stacking Faults
p.27

Early-Stage Reliability Evaluation of Passivation Stack and Termination Designs in SiC MPS Diodes
p.33

A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB
p.39

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure
p.47

Experimental Demonstration of Ultra-Fast SiC MOSFET Overload Protection Using Embedded Current and Temperature Sensors
p.53

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs
p.59

UIS Ruggedness of Parallel 4H-SiC MOSFETs
p.65

HomeSolid State PhenomenaSolid State Phenomena Vol. 361A Unique Failure Mode of SiC MOSFETs under...

A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB

Abstract:

Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, V_d and stress time dependent model.

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Periodical:

Solid State Phenomena (Volume 361)

Pages:

39-45

DOI:

https://doi.org/10.4028/p-CB1KRz

Citation:

Cite this paper

Online since:

August 2024

Authors:

Peter Moens*, Martin Domeij, Jean Francois Cano, Luc de Schepper, Stefan Verleye, Fredrik Allerstam

Keywords:

ALT-HTRB, Gate Oxide Degradation, Lifetime Model, SiC MOSFET

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Creative Commons CC BY 4.0

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* - Corresponding Author

References

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