Solid State Phenomena Vol. 360

Abstract: In this work, 4H-SiC p-i-n diodes with excellent single-pulse avalanche energy density (EAS) with positively beveled mesa termination have been demonstrated. The fabrication of this junction termination extension (JTE) obviates ion implantation and requires only etching process. With its uniform electric field and temperature distribution, the fabricated 4H-SiC p-i-n diodes show breakdown voltage (BV) of 886V (98.4% of the parallel-plane limit) and the inductive avalanche energy density of ~10.4J/cm²@1mH. Meanwhile, ruggedness of the avalanche breakdown has also been evidently promoted. The results confirm that this structure exhibits great capability potential in power applications.

Abstract: SiC MOSFETs still suffers from some open issues, such as the high density of defects existing at the SiC/ SiO₂ interface. In order to characterize such interface, a non-destructive investigation technique should be employed. In this work, we investigate the measurement of Gate capacitance with biased Drain. More in detail, the effect of frequency on such curves is considered. The analysis is performed using both in experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region which reduces its height as frequency increases.

Abstract: By using 4H-SiC packaged Charge-Balanced (CB) MOSFET, we have experimentally demonstrated a 3.3kV 4H-SiC common-drain bidirectional (BD) CB power MOSFET and measured its static and dynamic characteristics compared to its unidirectional counterpart. We show that the BD CB MOSFET conducts and blocks at the first and third quadrants with the appropriate gate bias with an on-state resistance double its unidirectional counterpart, while its switching energies are 12 (19) and 34 (12) mJ/cm² for BD CB MOSFET (UD CB MOSFET).

Abstract: In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Abstract: We quantitively compare the static and dynamic performance for high-voltage SiC bidirectional (BD) conventional and superjunction (SJ) DMOSFETs by using 3D TCAD simulations. We extract the specific on-resistance (R_ON,sp) and the total specific switching charge (Q_T,sp), which is a sum of the specific gate charge (Q_G,sp) and drain charge (Q_DS,sp) to quantify both the static and switching characteristics respectively. We also develop a new Figure-of-Merit (FoM), which is the product of R_ON,sp . Q_T,sp, to evaluate the overall performance. We show that the high-voltage 4H-SiC BD SJ DMOSFET has the best FoM with substantial (>58%) improvement, compared to the BD conventional DMOSFETs, which increases with increasing breakdown voltage.

Abstract: We demonstrated that the surge current capability of 3.3 kV Schottky-barrier-diode-embedded (SBD-embedded) SiC MOSFETs is equivalent to that of conventional SiC MOSFETs and three times higher than that of SiC SBDs. Furthermore, we revealed that the bipolar degradation attributed to the repetitive surge stress of high current density was negligible, which can be explained by the small total area of the expanded stacking faults (SFs) caused by the limited total period of conduction of the body diodes.

Abstract: A challenge in the development of Silicon carbide (SiC) gate turn-off thyristors lie in an uneven transient behaviour, necessitating expensive snubbers. To address these limitations and simplify circuit topology we present an optimized 16 kV n-type SiC integrated gate commutated thyristor (IGCT) design, which utilises a novel highly doped base strip (HDBS). A particular focus is on optimizing the gate commutation of the GCT during switching, and the trade-offs in the HDBS base design were investigated. The findings reveal that compared with conventional GCT design, the HDBS design under high current conditions recorded a 11.8% reduction in turn-off power losses. When simulating the device in a high-voltage scenario, the HDBS IGCT demonstrated a 3.9% reduction in turn-off power losses and an improved turn-on power loss performance. This resulted in a reduction of power losses by 12.1% and 2.3% in high current and high voltage conditions, respectively. In summary, the novel SiC HDBS IGCT design paves the way towards a secure, high current density, and low loss switching SiC thyristor device.

Abstract: In this work, variations in the channel length and gate oxide thickness are studied for the design optimization of 3300 V 4H-SiC based VDMOSFETs. For this, a batch of 3 wafers was processed and tested for key device characteristics. The results indicate shorter channel length of 0.5 μm leads to an increase in the drain leakage current, thus affecting the breakdown voltage as well. The thinner gate oxide at 50 nm demonstrates better control of threshold voltage with no variations in the gate leakage current distribution as compared to 65 nm.

Abstract: The short-circuit withstand time and on-resistance trade-off is investigated in 4H-SiC Power MOSFETs. We compare the static and short circuit withstand time results along with JFET width dependency and PWELL doping variation of MOSFET. We present that smaller Rds,on by wider JFET width and lighter doped PWELL results in worse short circuit withstand time.

Abstract: Recently, silicon carbide (SiC) power modules of the 3.3 kV voltage class became available and are a promising candidate to replace silicon power modules in traction applications. However, the more than three times higher Young’s Modulus compared to silicon leads to a reduced lifetime under thermo-mechanical stress. This could pose a significant obstacle in their implementation, since traction applications are particularly demanding in their mission profiles with respect to load cycling, but also to environmental conditions. Thus, the thermo-mechanical stress is not just limiting the lifetime itself, but might also promote the humidity induced degradation due to delamination or micro-cracks. In this work, multiple power cycling tests at different temperature swings on 3.3 kV SiC MOSFET chips in a power module were performed, to assess their ruggedness under thermo-mechanical stress. Before or afterwards, these modules were tested under standard HV-H3TRB conditions to verify the interaction between thermo-mechanical and humidity stress on the robustness of the modules.