Solid State Phenomena Vol. 358

Abstract: Bipolar degradation of the intrinsic bipolar body diode is one of the most important reliability problems associated with SiC MOSFET. In this paper, a voltage adjustable diode (VAD) integrated SiC trench MOSFET (VAD-TMOS) with barrier control gate (BCG) is proposed to overcome this issue. Compared to the intrinsic bipolar body diode of conventional SiC trench MOSFET (C-TMOS), VAD has 57% reduction of the on-state voltage drop. Furthermore, the reverse recovery charge (Q_rr) of VAD-TMOS is only 1.21 μC/cm², whereas the value of C-TMOS is 3.84 μC/cm². The miller charge (Q_gd) of VAD-TMOS is reduced by about 6 × in comparison with that of C-TMOS owing to the reduction of the overlap region of gate and drain terminal. The better third quadrant and fast switching capability make SiC VAD-TMOS a potential candidate as a next generation of power switch.

Abstract: Gate oxide reliability is a challenge in SiC MOSFETs particularly due to the presence of high electric field in the dielectric during device operation and blocking, and SiC/SiO₂ interfaces suffer from a high density of traps and defects that can cause charge trapping and threshold voltage shift. Highly accelerated gate bias testing can be used for testing gate field effects on device reliability/stability, but care must be taken that the high acceleration biases do not invoke failure mechanisms that fall outside of normal device operation conditions. In this work, we attempt to address that aspect of high voltage gate tests in terms of threshold voltage instability and perform a comparative analysis between commercially available planar and trench SiC MOSFETs.

Abstract: An Al₂O₃/LaAlO₃/SiO₂ gate stack is designed and implemented on various trench-gate channel planes for high-performance trench power MOSFETs. The designed high-k gate stack achieves a significant enhancement in the gate blocking capability (~1.73X) and maintains a low interface state density (D_it), in comparison to the SiO₂­ gate. Moreover, owing to the implementation of the high-k gate stack, the high-k trench gate MOSFETs conduct a drain current of approximately 1.3 times larger than that of the SiO₂ trench gate MOSFETs on all 24 channel planes at the same overdrive voltage (V_gs-V_th) of 10 V. An analysis of the mobility limiting mechanisms on different channel planes reveals that the highest channel mobility on the (1120) channel plane is primarily due to its largest Coulomb scattering mobility and surface roughness scattering mobility.

Abstract: Channel density design guidelines for SiC trench-gate MOSFETs with low switching loss, and high short-circuit and avalanche capabilities were proposed. The cell and grounding region pitches were used as parameters to control the channel density to investigate the parameter dependence of each transient property. The results suggest a clear difference in the dependence of switching loss reduction and short-circuit/avalanche capability increase on these parameters; however, the extents of dependence of specific on-resistance on the controlling parameters were comparable. The reduction in the grounding region pitch contributed to faster charging of the parasitic drain-source capacitance, which was effective in improving transient characteristics, such as dV/dt at turn-off, and saturation current at short-circuit. Furthermore, a reduction in this distance increased the area-flowing avalanche current and hence, an increase in the avalanche energy. The influence of the two design parameters in effectively improving the trade-off between each transient characteristic and the specific on-resistance was summarized.

Abstract: Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are successfully replacing traditional silicon insulated gate bipolar transistors (Si IGBTs) in power applications. Nonetheless, two crucial challenges persist: gate-oxide reliability and a reduced short circuit (SC) withstand time. This paper explores a novel MOSFET structure, which is designed to address these concerns and compares it with existing designs through extensive 3D TCAD simulations. The proposed MOSFET structure features a p-region under the gate, providing a unique configuration for improved performance during SC events. This novel structure is then compared to two commercially realized MOSFET structures. Our structure has a superior on-state performance with a specific resistance of 1.48 mΩ /cm², showing an improvement by 25 % and 15 %, respectively. It also increases the blocking capability by 100 V and SC withstand time in comparison to the double-trench MOSFET.

Abstract: We present a revised channel mobility model for 4H-SiC MOSFETs. Mobility measurements are performed on 4H-SiC lateral MOSFET test structures in the temperature range of 25-175 °C. We observe that the temperature and P-well concentration dependence of channel mobility cannot be predicted by popular mobility models available within commercial TCAD tools. A careful investigation revels that channel mobility components need to be revised and replaced using a comprehensive model that accurately describes the predominant scattering mechanisms. We present a well calibrated channel mobility model for 4H-SiC using a revised treatment of bulk, surface roughness and surface phonon components. An excellent agreement with measured data is obtained using this model, making it more suitable for predictive device simulation using TCAD tools.

Abstract: In this work, we investigate the use of reflectance spectroscopy as an accurate, fast, and non-destructive method for measuring the thickness of transparent layers, such as SiO₂, with thicknesses below 200 nm for microelectronic applications. To this end, we fabricated different oxides and analyzed their reflectance spectra using reflectance spectroscopy. The results were compared to theoretical reflectance spectra to validate the method. We introduce key factors to ensure accurate measurement by modeling the reflectance spectra of thin oxide layers with thicknesses ≥ 15 nm on 4H-SiC using the transfer matrix method (TMM).

Abstract: Thick 4H-SiC epilayers have be grown with n-type and p-type doping in the range 1x10¹⁴ cm^‑3 to mid 1x10¹⁸ cm^‑3, with the purpose of investigating the influence of doping on carrier lifetime. Growth conditions were identical for all grown epilayers, except for the dopant gas flow rates. A drastic decrease in carrier lifetime was observed with increasing doping level, in both n-type and p-type layers. The decrease in lifetime could not be related to the Z_1/2 center but are rather due to an enhanced effect of direct band-to-band and Auger recombination’s (AR) at higher doping levels. Calculations of Auger coefficients for the recombination’s are indicating Auger recombination’s as the main recombination mechanism at the highest doping levels. Indications are made stronger from the temperature dependence of Auger coefficients. An increased background intensity arises around 400 K during temperature dependent time-resolved photoluminescence measurements of n-type epilayers are observed and are thought to be related to boron impurities.

Abstract: The short-circuit (SC) performance of Silicon Carbide (SiC) power MOSFETs has been extensively characterized in recent years. During a SC event, a SiC power MOSFET experiences a thermo-mechanical (TM) stress originating from a high temperature change during the SC event and the different coefficients of thermal expansions (CTEs) of source metallization, polySilicon gate, SiC and gate-source insulator. High temperature and TM stress cause the aluminum source metallization to melt, and a crack to form and grow within the gate-source insulation, leading to a short connection between the gate and source terminals typically referred to as fail-to-open (FTO) failure mode. This paper presents a 2-D thermo-mechanical (TM) model of a 2-D MOSFET half-cell for assessing the TM stress in the gate-source insulating layer during SC including the phase change behavior and the temperature-dependent properties of the source metallization. The developed modeling approach allows to assess how different metallization thicknesses and materials affect the TM stress of the gate-source insulation and, hence, enables the development of device design guidelines for improving SC withstand time of SiC power MOSFETs.

Abstract: This paper proposes performance evaluation of SiC MOSFETs power devices introducing in the device layout some specific design to achieve desired value of intrinsic gate resistance. This aspect can be helpful to eliminate external components such as gate resistance, saving space and cost, considering the application of the gate driver directly connected to the power device. Description about the layout modification of the device die is presented and dedicated simulation approach is set and exploited to predict the signal propagation on the die while verifying the gate resistance defined by the new layout structure. Experimental results including switching losses evaluations performed with double pulse tests sequence with half-bridge converter realized with new SiC MOSFETs devices, are also reported in the paper.