Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

Philip G. Neudeck; Liang Yu Chen; Lawrence C. Greer; David J. Spry; Norman F. Prokop; Dorothy Lukco; Michael J. Krasowski; Gary W. Hunter

doi:10.4028/p-u3Mieo

Paper Titles

Investigation of Potential Impact of Nitridation Process on Single Event Gate Rupture Tolerance in SiC MOS Capacitors
p.1

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board
p.7

Coupled Non-Destructive Methods, Kelvin Force Probe Microscopy and µ-Raman to Characterize Doping in 4H-SiC Power Devices
p.13

Concept and Technology for Full Monolithic MOSFET and JBS Vertical Integration in Multi-Terminal 4H-SiC Power Converters
p.23

Comparing 4H-SiC NPN Buffer Layers by Epitaxial Growth and Implantation for Neural Interface Isolation
p.31

Modeling the Charging of Gate Oxide under High Electric Field
p.37

Complementary Two Dimensional Carrier Profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy
p.45

Temperature Dependence of 4H-SiC Gate Oxide Breakdown and C-V Properties from Room Temperature to 500 °C
p.51

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Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

Abstract:

This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.

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