Comparing 4H-SiC NPN Buffer Layers by Epitaxial Growth and Implantation for Neural Interface Isolation

Scott Greenhorn; Edwige Bano; Valerie Stambouli; Konstantinos Zekentes

doi:10.4028/p-jqCtr5

Paper Titles

Investigation of Potential Impact of Nitridation Process on Single Event Gate Rupture Tolerance in SiC MOS Capacitors
p.1

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board
p.7

Coupled Non-Destructive Methods, Kelvin Force Probe Microscopy and µ-Raman to Characterize Doping in 4H-SiC Power Devices
p.13

Concept and Technology for Full Monolithic MOSFET and JBS Vertical Integration in Multi-Terminal 4H-SiC Power Converters
p.23

Comparing 4H-SiC NPN Buffer Layers by Epitaxial Growth and Implantation for Neural Interface Isolation
p.31

Modeling the Charging of Gate Oxide under High Electric Field
p.37

Complementary Two Dimensional Carrier Profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy
p.45

Temperature Dependence of 4H-SiC Gate Oxide Breakdown and C-V Properties from Room Temperature to 500 °C
p.51

Detection of Very Fast Interface Traps at 4H-SiC/AlN and 4H-SiC/Al₂O₃ Interfaces
p.59

HomeSolid State PhenomenaSolid State Phenomena Vol. 358Comparing 4H-SiC NPN Buffer Layers by Epitaxial...

Comparing 4H-SiC NPN Buffer Layers by Epitaxial Growth and Implantation for Neural Interface Isolation

Abstract:

4H Silicon Carbide multichannel neural interface devices using NPN junctions for channel isolation were fabricated using four different doping structures. Two devices used thicker, lower-doped epitaxial layers, one used thin, highly-doped implanted layers implanted into a N epilayer, and one used thin-highly-doped implanted layers into an N substrate. The devices were characterized in terms of resistance, charge delivery, leakage current through the substrate, and crosstalk between channels. The thickest, lower-doped epitaxial layers performed best, resulting in great isolation and good performance. While the implanted layers showed high charge delivery, their resistance is reduced due to the thin layers and the isolation is particularly poor.

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Periodical:

Solid State Phenomena (Volume 358)

Pages:

31-35

DOI:

https://doi.org/10.4028/p-jqCtr5

Citation:

Cite this paper

Online since:

August 2024

Authors:

Scott Greenhorn*, Edwige Bano, Valerie Stambouli, Konstantinos Zekentes

Keywords:

Isolation, Neural Interface, P-N Junction

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Creative Commons CC BY 4.0

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* - Corresponding Author

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