Influence of Active Area Etching Method on the Integrity of Gate Oxide on 4H-SiC

Chia Hua Wang; Li Jung Lin; Chia Lung Hung; Yi Kai Hsiao; Bing Yue Tsui

doi:10.4028/p-j9uFNJ

Paper Titles

Increasing Mobility in 4H-SiC MOSFETs with Deposited Oxide by In-Situ Nitridation of SiC Surface
p.157

Demonstrating SiC In Situ Rounded Trench Processing Technologies for Future Power Trench MOSFET Applications
p.163

High Mobility 4H-SiC P-MOSFET via Ultrathin ALD B₂O₃ Interlayer between SiC and SiO₂
p.171

Quality Improvement of SiC Substrate Surface with Using Non-Abrasive CMP Slurry
p.181

Addition of Transition Metal Ion CMP Slurry for Forming Ultra-Flat SiC Crystal
p.187

Increasing 4H-SiC Trench Depth by Improving the Dry Etch Selectivity towards the Oxide Hard Mask
p.193

A Comparison between Different Post Grinding Processes on 4H-SiC Wafers
p.201

Influence of Active Area Etching Method on the Integrity of Gate Oxide on 4H-SiC
p.211

High-K Gate Dielectric for High-Performance SiC Power MOSFET Technology with Low Interface Trap Density, Good Oxide Lifetime (t_tddb≥ 10⁴s), and High Thermal Stability (≥ 800 °C)
p.217

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Influence of Active Area Etching Method on the Integrity of Gate Oxide on 4H-SiC

Abstract:

Etching active area by dry etching method can precisely control the length and width of the devices, but it may damage the SiC surface. In this paper, we fabricated metal-oxide-semiconductor capacitors (MOSC) using different etching methods to compare the effect of etching methods on the SiO₂/SiC interface and dielectric breakdown. It is observed that dry etching will degrade the surface roughness of SiC and the interface state density at the SiO₂/SiC interface. Post-oxidation NO annealing cannot passivate the interface effectively. The breakdown field of gate oxide on the dry etched sample is also degraded. These results indicate that dry etching of SiC surface should be avoided when fabricating MOS devices.

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