Analytical Threshold Voltage Models for Strained Si/Strained Si1-xGex/Relaxd Si1-yGey PMOSFET

Shan Shan Qin; He Ming Zhang; Hui Yong Hu; Xiao Yan Wang; Guan Yu Wang

doi:10.4028/www.scientific.net/AMM.110-116.5447

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 110-116Analytical Threshold Voltage Models for Strained...

Analytical Threshold Voltage Models for Strained Si/Strained Si_1-xGe_x/Relaxd Si_1-yGe_y PMOSFET

Abstract:

Threshold voltage models for both buried channel and surface channel for the dual-channel strained Si/strained Si_1-xGe_x/relaxd Si_1-yGe_y(s-Si/s-SiGe/Si_1-yGe_y) p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) are presented in this paper. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel, because the hole mobility in the buried channel is higher than that the surface channel. They offer a good accuracy as compared with the results of device simulator ISE.

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Periodical:

Applied Mechanics and Materials (Volumes 110-116)

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5447-5451

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.110-116.5447

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Online since:

October 2011

Authors:

Shan Shan Qin, He Ming Zhang, Hui Yong Hu, Xiao Yan Wang, Guan Yu Wang

Keywords:

Dual-Channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Strained Si, Strained SiGe, Threshold Voltage

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References

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