A High Efficiency CMOS Power Amplfieir with a Diode Linearizer and Voltage Combining Transformers
This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.
K. J. Kim et al., "A High Efficiency CMOS Power Amplfieir with a Diode Linearizer and Voltage Combining Transformers", Applied Mechanics and Materials, Vols. 110-116, pp. 5500-5504, 2012