Steep-Slope Devices: Prospects and Challenges

Abstract:

In this work, an overview is given on the prospects and challenges of two novel device concepts,namely the Tunnel FET (TFET) and the Superlattice FET (SL-FET). The optimization effort ofhomo- and hetero-junction TFETs carried out so far shows that these devices can provide an advantageover CMOS FETs only for very-low power and low-performance niche applications, so long asthe supply voltage is scaled below 300 mV. The required materials for homojunction TFETs are lowbandgap semiconductors, such as InAs and InGaAs; for heterojunction TFETs the best semiconductorpair appears to be (Al)GaSb-InAs. Several technological problems are still unsolved: poor qualityof the oxide interface with III-V materials and device variability are probably the most important. The SL-FET represents in principle a better device concept, as it provides outstanding performance and meets nearly all targets of the high performance (HP), low operating power (LOP) and low standby power (LSTP) of the ITRS at V_DD = 0.4V. A suitably-designedInGaAs-InAlAs SL-FET has turned out to provide the best simulation results. However, the fabricationprocess of SL-FETs is much more complex, as it requires molecular epitaxy to deposit multiplelayers with a very strict control of their nanometric thickness. Besides, vertical devices can poseunexpected problems as far as layout organization and parasitics are concerned.

• Periodical: Journal of Nano Research (Volume 39)
• Pages: 3-16
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.39.3
• Online since: February 2016
• Authors: Elena Gnani*, Emanuele Baravelli, Pasquale Maiorano, Antonio Gnudi, Susanna Reggiani, Giorgio Baccarani
• Keywords: Low-Power Electronics, Nanowire Field-Effect Transistor (NW-FET), Post-CMOS Devices, Steep-Slope Transistors, Superlattice-FET, Unnel-FET

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