Charge Trap Mechanism in Hybrid Nanostructured (YMnO₃) Metal-Oxide-Semiconductor (MOS) Devices

Abstract:

Hybrid nanostructured Metal Oxide Semiconductor (MOS) capacitor was fabricated on silicon substrates (n-type) using chemical solution deposition with YMnO3 as an oxide layer. Electrical properties of MOS capacitor have been investigated with frequency dependence capacitance-voltage (C-V) characterization. The surface morphology of deposited layer was studied using the Atomic Force Microscopy (AFM). Hysteresis in the C-V loop and change in the values of Cminimum were described by a charge trap mechanism in the multiferroic oxide layer of MOS devices. While anomalous behavior in saturation capacitance in the inversion as well as in accumulation region and a shift in threshold voltage (V_T) were explained in the vicinity of frequency depended Debye length (L_Debye).

• Periodical: Journal of Nano Research (Volume 42)
• Pages: 92-99
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.42.92
• Online since: July 2016
• Authors: Dr Jaysukh Markna*, Davit Dhruv, K Rathod, Chirag Savaliya, T.M. Shiyani, Dhiren Pandya, Ashvini D. Joshi, N.A. Shah
• Keywords: Atomic Force Microscopy, Chemical Solution Deposition, Metal-Oxide-Semiconductor (MOS) Capacitor, Thin Film

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