Key Engineering Materials Vol. 1055

Abstract: A charge-imbalanced P-pillar distribution termination (D3) is proposed for 1500 V-class 4H-SiC superjunction (SJ) devices. By combining a junction termination extension (JTE)-based termination with gradually widened P-pillar spacing, the design effectively suppresses edge electric field crowding and enhances device reliability. TCAD simulations show that D3 achieves comparable blocking capability while exhibiting significantly improved robustness against charge imbalance, oxide charge density, and JTE dose deviations, demonstrating superior process margin and reliability. With relaxed process sensitivity and an efficient structure, D3 presents a promising approach for high-voltage 4H-SiC SJ device fabrication.

Abstract: We experimentally demonstrated a ~2x on-current enhancement in VDMOSFET fabricated in a standard 3300 V-rated 4H-SiC process. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A 5x10³-10⁴ ratio between the on-current gain and the p-well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Abstract: This study proposes a refilled PMOS SiC trench MOSFET (RPTMOS) design with integrated parasitic PMOS clamping transistors to mitigate single-event burnout (SEB) susceptibility. The configuration of the core epi-refill process to realize the proposed RPTMOS is also demonstrated. Through systematic TCAD simulations, we analyze the transient lattice temperature, electric field distribution, and current density dynamics under heavy-ion irradiation (LET = 19.0 MeV·cm²/mg, Drain DC Bias V_D = 500 V). The optimized structure features a grounded parasitic PMOS clamp formed by the P-connect, P-bottom, and N-drift regions, which enables efficient hole extraction and suppresses electric field crowding at the gate oxide corner. Comparative simulations reveal that the proposed design reduces peak lattice temperatures and elevates the SEB withstand voltage by ~20%. Parametric studies further demonstrate that increasing the P-connect thickness (200 Å → 400 Å) significantly enhance radiation hardness, proves the pivotal contribution from the parasitic PMOS. The findings offering a viable pathway for radiation-hardened SiC power devices in aerospace and high-energy applications.

Abstract: A comparative study of state-of-the-art commercial 1200V trench-gate, planar-gate, and trench-assisted planar Silicon Carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance (R_ON,SP), gate leakage (I_GSS​), drain leakage (I_DSS​), breakdown voltage (BV_DSS​), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25 °C and 175 °C while the single-pulse and repetitive short-circuit capability is evaluated under hard switching fault (HSF) under 25 °C.

Abstract: SiC GTOs, with high current handling capability, are promising for high-voltage and high-power applications, but they also have temperature-related reliability issues, so real-time junction temperature monitoring is needed. In this paper, a novel 4H-SiC gate turn-off thyristor (GTO) structure with integrated temperature sensor is proposed. The proposed sensor is compatible with the SiC GTO process and allows for real-time temperature monitoring. TCAD simulation results show that the integrated sensor has a high sensitivity of 1.64mV/K and linearity of 0.99891, the temperature sensor monitors the internal temperature of the GTO device in real time with an error of no more than 2 K during complete GTO switching. This new structure is conducive to enhancing the reliability of SiC thyristor applications and system miniaturization.