Key Engineering Materials Vol. 1054

Abstract: The pursuit of ever-higher system efficiency and power density in power electronic applications paves the way for an increased utilization of wide bandgap semiconductor devices such as silicon carbide (SiC) MOSFETs, due to reduced conduction and switching losses compared to silicon. For real-world application reliable operation along its lifetime is of utmost importance. To assure robust operation in electric drives and traction inverters SiC MOSFETs are switched bipolar to prevent parasitic turn on. Recently, it has been shown that not only bias temperature instability, but also gate-switching instability in bipolar switched applications has to be considered as a reliability concern for SiC MOSFET. While in gate switching stress tests usually only critically damped conditions are investigated irrespective of rise and fall times, in real-world applications gate voltage overshoots may occur and a broad variety of slew rates may be used depending on the individual power converter design. Therefore, this work investigates the influence of gate voltage overshoot and voltage slopes on threshold voltage aging using high frequencies and online degradation monitoring. It is shown that overshoots have a dominating impact on the overall degradation, while the gate voltage slope impacts minorly.

Abstract: This paper presents the development and evaluation of a 1.2 kV SiC MOSFET-based Positive Temperature Coefficient (PTC) controller designed for energy-efficient heating applications in electric vehicles (xEVs). To address the increasing demand for higher-voltage battery systems in modern xEVs, a PTC controller utilizing wide bandgap (WBG) semiconductor technology was developed. The proposed system leverages a 1.2 kV SiC MOSFET to enable high-frequency operation up to 20 kHz, thereby mitigating audible noise issues by operating beyond the human hearing range. Unlike conventional IGBT-based controllers, which exhibit significant limitations at high switching frequencies, the SiC MOSFET-based controller demonstrates reliable high-frequency operation, reduced switching losses, and improved overall efficiency. Experimental validation confirms that the proposed approach not only ensures low-noise heating operation but also enhances energy efficiency, making it a promising solution for next-generation xEV thermal management systems.

Abstract: In this work, the power cycling capability of discrete SiC MOSFETs of seven manufacturers is investigated. The results show that even nominally similar devices can exhibit substantially different power cycling capabilities. The differences among the tested devices involve the scaling factor and the slope of the lifetime curves, but also the dependence of the baseline temperature. Furthermore, some devices exhibit a considerable increase in power cycling performance towards lower temperature swings, which cannot be characterized properly by power cycling tests at typical test conditions with much larger temperature swings. Thus for a proper assessment of the power cycling performance, multiple tests at suitable test conditions are necessary to obtain meaningful results.

Abstract: The reliability of silicon carbide (SiC) MOSFETs under alternating current bias temperature instability (AC-BTI) is a critical issue for power electronics. Previous studies show inconsistent temperature dependence of threshold voltage drift (ΔV_th) induced by AC-BTI and have not conducted tests at temperatures below room temperature. In this study, ΔV_th was measured in four commercially available SiC MOSFETs across a wide temperature range (-40°C to 150°C) under bipolar AC stress up to 10¹¹ cycles. Most devices showed larger ΔV_th at lower temperatures, while one device exhibited increased ΔV_th also at high temperatures. These results may be explained by interface recombination mechanisms, with the device-dependent behavior possibly attributed to structural differences. The findings suggest the need for sub-room temperature testing to identify worst-case degradation scenarios in SiC MOSFETs.

Abstract: This study investigated the reliability challenges of SiC MOSFETs under continuous dual-bias stress conditions in electric vehicle (EV) applications. Accelerated dual-bias time-dependent dielectric breakdown (DB-TDDB) tests were performed on 1.2kV SiC MOSFETs by applying a negative gate-source voltage and a high drain-source voltage simultaneously. Experimental analysis and TCAD simulations revealed a nonlinear coupling effect between gate and drain biases, leading to a spatial relocation of the maximum gate oxide electric field under dual-bias conditions. An improved dual-acceleration-factor E-model was proposed to characterize this behavior. Based on this model, the projected lifetime at 1 ppm failure rate is 5.11×10¹³ hours, exceeding the 20-year automotive standard (AEC-Q101) by several orders of magnitude. Furthermore, failure analysis identified edge-thinning and JFET-region effects as two primary degradation mechanisms affecting gate oxide reliability, and corresponding process and design optimizations are proposed to mitigate this vulnerability. The findings offer critical insights for improving the reliability of SiC MOSFETs in EV applications under prolonged dual-bias stress.

Abstract: The long-term reliability of silicon carbide MOSFETs is critically influenced by the stability of the gate oxide, which is susceptible to degradation due to high defect densities at the oxide-semiconductor interface. This work presents a comprehensive investigation of gate oxide degradation in next-generation SiC MOSFETs, comparing planar and trench device topologies under both static and dynamic stress conditions. Time-dependent dielectric breakdown measurements reveal degradation phases that are strongly dependent on device topology. Comparative analysis of various gate stress methodologies shows that dynamic switching stress exerts a more pronounced impact on trench devices than on planar devices. Thus, highlighting the need of tailoring reliability test protocols to the specific device topology, rather than adopting a generalized approach.

Abstract: This paper presents a comparative analysis of 1200 V Silicon Carbide (SiC) MOSFETs characterized at bare die level and in TO-247 packaging. Static parameters including transconductance (g_m), drain leakage current (I_DS-OFF), output (I_DS-V_DS) and transfer characteristics (I_DS-V_GS), gate threshold voltage (V_GS(th)) and on-state resistance (R_DS(on)) are examined. Results show that the TO-247 package introduces parasitic resistance/inductance and higher thermal impedance, leading to disrupted g_m, though lower leakage I_DS-OFF, shifted V_GS(th), and elevated R_DS(on). The study quantifies the discrepancy between intrinsic die behavior and packaged device performance, underscoring the need to de-embed packaging effects for accurate device modelling and optimization.

Abstract: This work investigates the short-circuit (SC) robustness of 1200 V SiC MOSFETs from two different manufacturers (M1: trench-gate, M2: planar-gate) up to their destruction limits. Both devices, packaged in TO-247 4-pin housings with a nominal on-state resistance (R_ds,on) of 80 mΩ, were systematically tested under a gate-source voltage of V_GS,on =15 V and at a fixed DC-link voltage of 800 V. In addition to determining the SC withstand capability, the study focuses on the influence of the negative gate bias (V_GS,off ​) on device robustness. Results show that SC capability and dominant failure mechanisms are strongly dependent on gate technology as well as on the applied V_GS,off ​. Trench-gate M1 devices primarily fail due to gate oxide degradation under strong negative bias, while planar-gate M2 devices exhibit failures linked to parasitic BJT activation at SC turn-off or thermal runaway at V_GS,off ​= 0 V. Additionally, TCAD simulations closely reproduce the measured trends and provide physical insight into the failure mechanisms. The experimental–simulation approach establishes a comprehensive understanding of SC robustness limits and failure types in state-of-the-art SiC MOSFET technologies.

Abstract: As a switching device, a SiC MOSFET operates under high-frequency and fast switching edges, facing severe reliability challenges in the dynamic mode. The degradation of electrical characteristics of SiC MOSFETs under high-voltage dynamic switching conditions is systematically investigated in this study. It is found that the threshold voltage and on-resistance exhibit initial transient degradation but they both stabilize, with changes remaining within ±5%. They show no dependence on the pulse amplitude, frequency, duty cycle, or temperature. This is attributed to the shielding effect of the P-well structure on the electric field in the channel region, which suppresses the continuous accumulation of interface charges. Additionally, the body diode voltage drop shows no significant shift, indicating that the dynamic reverse bias stress has no substantial impact on the n-drift region. However, the blocking capability can degrade and the degradation trajectory exhibits cross-coupling effects of multiple factors. The rate of degradation is positively correlated with the pulse voltage amplitude, frequency, duty cycle, and test temperature. As these stressors increase, carriers gain higher energy in the couple electro-thermal fields, leading to enhanced charge injection efficiency and trapping depth, increased interface charge accumulation, and localized electric field distortion, resulting in nonlinear degradation of the device's blocking capability. This study reveals the degradation mechanisms of SiC MOSFET under dynamic stress conditions, providing a theoretical basis for the optimization of interface engineering and dynamic operation adaptation design of high-reliability power devices.