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HomeKey Engineering MaterialsKey Engineering Materials Vol. 1054Impact of the Negative Gate Bias on Short-Circuit...

Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

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Abstract:

This work investigates the short-circuit (SC) robustness of 1200 V SiC MOSFETs from two different manufacturers (M1: trench-gate, M2: planar-gate) up to their destruction limits. Both devices, packaged in TO-247 4-pin housings with a nominal on-state resistance (R_ds_,on) of 80 mΩ, were systematically tested under a gate-source voltage of V_GS,on =15 V and at a fixed DC-link voltage of 800 V. In addition to determining the SC withstand capability, the study focuses on the influence of the negative gate bias (V_GS,off ) on device robustness. Results show that SC capability and dominant failure mechanisms are strongly dependent on gate technology as well as on the applied V_GS,off . Trench-gate M1 devices primarily fail due to gate oxide degradation under strong negative bias, while planar-gate M2 devices exhibit failures linked to parasitic BJT activation at SC turn-off or thermal runaway at V_GS,off = 0 V. Additionally, TCAD simulations closely reproduce the measured trends and provide physical insight into the failure mechanisms. The experimental–simulation approach establishes a comprehensive understanding of SC robustness limits and failure types in state-of-the-art SiC MOSFET technologies.

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Robustness and Reliability of SiC MOSFET Devices, SiC MOSFET Power Modules

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Periodical:

Key Engineering Materials (Volume 1054)

Pages:

55-67

DOI:

https://doi.org/10.4028/p-HwDA3m

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Online since:

May 2026

Authors:

Madhu Lakshman Mysore*, Rahul Vijaybhai Chavda, Josef Lutz, Thomas Basler

Keywords:

Gate-Leakage, npn Bjt Activation, SC Failures, Short-Circuit Robustness, TCAD, Thermal Runaway

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Creative Commons CC BY 4.0

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* - Corresponding Author

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